9edf38ef1f
In order to access secure device register space the cpu needs to have the page tables marked as secure memory. In addition the page tables need to live within secure memory otherwise the accesses default to non-secure. Therefore move the page tables to the trustzone region. Remove the TTB_* config options as well as removing the TTB reservations from coreboot's resource list. BUG=chrome-os-partner:31355 BUG=chrome-os-partner:31356 BRANCH=None CQ-DEPEND=CL:213140 TEST=Built and booted into kernel. Change-Id: I1fc8dda932c36935f8523792bc1147f6b0743d11 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1522a83bb57e33749843d5b3ea5545ded97a3953 Original-Change-Id: Ia4b9d07ef35500726ec5b289e059208b9f46d025 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/213141 Reviewed-on: http://review.coreboot.org/8994 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
114 lines
2.2 KiB
Text
114 lines
2.2 KiB
Text
config SOC_NVIDIA_TEGRA132
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bool
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default n
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select ARCH_BOOTBLOCK_ARMV4
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select ARCH_VERSTAGE_ARMV4
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select ARCH_ROMSTAGE_ARMV4
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select ARCH_RAMSTAGE_ARMV8_64
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select ARM_LPAE
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select DYNAMIC_CBMEM
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select BOOTBLOCK_CONSOLE
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select HAVE_MONOTONIC_TIMER
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select HAVE_HARD_RESET
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select HAVE_UART_SPECIAL
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select HAVE_UART_MEMORY_MAPPED
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select EARLY_CONSOLE
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select ARM_BOOTBLOCK_CUSTOM
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if SOC_NVIDIA_TEGRA132
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config BOOTBLOCK_CPU_INIT
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string
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default "soc/nvidia/tegra132/bootblock.c"
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help
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CPU/SoC-specific bootblock code. This is useful if the
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bootblock must load microcode or copy data from ROM before
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searching for the bootblock.
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config BOOTBLOCK_ROM_OFFSET
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hex
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default 0x0
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config CBFS_HEADER_ROM_OFFSET
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hex "offset of master CBFS header in ROM"
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default 0x40000
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config CBFS_ROM_OFFSET
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hex "offset of CBFS data in ROM"
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default 0x40080
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config BOOTBLOCK_BASE
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hex
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default 0x40020000
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config ROMSTAGE_BASE
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hex
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default 0x40025000
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config SYS_SDRAM_BASE
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hex
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default 0x80000000
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config RAMSTAGE_BASE
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hex
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default 0x80200000
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config BOOTBLOCK_STACK_TOP
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hex
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default 0x40020000
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config BOOTBLOCK_STACK_BOTTOM
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hex
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default 0x4001c000
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config ROMSTAGE_STACK_TOP
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hex
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default 0x40020000
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config ROMSTAGE_STACK_BOTTOM
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hex
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default 0x4001c000
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config RAMSTAGE_STACK_TOP
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hex
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default 0x80020000
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config RAMSTAGE_STACK_BOTTOM
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hex
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default 0x8001c000
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config CBFS_CACHE_ADDRESS
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hex "memory address to put CBFS cache data"
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default 0x40006000
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config CBFS_CACHE_SIZE
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hex "size of CBFS cache data"
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default 0x00016000
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config CONSOLE_PRERAM_BUFFER_BASE
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hex "memory address of the CBMEM console buffer"
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default 0x40004020
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config MTS_DIRECTORY
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string "Directory where MTS microcode files are located"
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default "3rdparty/cpu/nvidia/tegra132/current/prod"
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help
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Path to directory where MTS microcode files are located.
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config TRUSTZONE_CARVEOUT_SIZE_MB
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hex "Size of Trust Zone region"
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default 0x1
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help
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Size of Trust Zone area in MiB to reserve in memory map.
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config BOOTROM_SDRAM_INIT
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bool "SoC BootROM does SDRAM init with full BCT"
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default n
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help
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Use during Ryu LPDDR3 bringup
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# Default to 700MHz. This value is based on nv bootloader setting.
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config PLLX_KHZ
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int
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default 700000
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endif
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