842f76c90c
I2C6 has a special mux in the SOR/DC domain, so there's a ton of devices that need to be clocked, SOR unpowergated, and then the I2C6 muxing done in the DPAUX_HYBRID_PADCTL register. BUG=none BRANCH=none TEST=none, built rush/ryu AOK Change-Id: Ibeeda763b7fb30fabaee85d03fbf7d5efb42a30a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0b4da98e20a89b045f2d5b5033a27cd7ab855f35 Original-Change-Id: I4aaa74ef1b3009da621d1a2ef6f79de8ebf545e2 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/212887 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8992 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
98 lines
2.8 KiB
C
98 lines
2.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (c) 2014, NVIDIA CORPORATION.
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* Copyright 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <soc/addressmap.h>
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#include <soc/clock.h>
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#include <soc/padconfig.h>
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#include <soc/nvidia/tegra/i2c.h>
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#include <soc/nvidia/tegra132/power.h>
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#include <soc/nvidia/tegra132/clk_rst.h>
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#include "delay.h"
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#define I2C6_BUS 5
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#define I2C6_PADCTL 0xC001
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#define DPAUX_HYBRID_PADCTL 0x545C0124
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static struct tegra_pmc_regs * const pmc = (void *)TEGRA_PMC_BASE;
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static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
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static int partition_clamp_on(int id)
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{
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return read32(&pmc->clamp_status) & (1 << id);
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}
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static void remove_clamps(int id)
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{
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if (!partition_clamp_on(id))
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return;
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/* Remove clamp */
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write32((1 << id), &pmc->remove_clamping_cmd);
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/* Wait for clamp off */
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while (partition_clamp_on(id))
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;
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}
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static void enable_sor_periphs(void)
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{
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u32 lclks = CLK_L_HOST1X;
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u32 hclks = CLK_H_MIPI_CAL | CLK_H_HDMI | CLK_H_DSI;
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u32 uclks = CLK_U_DSIB;
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u32 wclks = CLK_W_DP2 | CLK_W_HDA2HDMICODEC;
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u32 xclks = CLK_X_DPAUX | CLK_X_SOR0 | CLK_X_HDMI_AUDIO;
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clock_enable(lclks, hclks, uclks, 0, wclks, xclks);
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/* Give clocks time to stabilize. */
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udelay(IO_STABILIZATION_DELAY);
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}
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static void unreset_sor_periphs(void)
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{
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u32 lclks = CLK_L_HOST1X;
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u32 hclks = CLK_H_MIPI_CAL | CLK_H_HDMI | CLK_H_DSI;
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u32 uclks = CLK_U_DSIB;
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u32 wclks = CLK_W_DP2 | CLK_W_HDA2HDMICODEC;
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u32 xclks = CLK_X_DPAUX | CLK_X_SOR0 | CLK_X_HDMI_AUDIO;
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clock_clear_reset(lclks, hclks, uclks, 0, wclks, xclks);
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}
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void soc_configure_i2c6pad(void)
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{
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/*
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* I2C6 on Tegra124/132 requires some special init.
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* The SOR block must be unpowergated, and several
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* display-based peripherals must be clocked and taken
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* out of reset so that a DPAUX register can be
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* configured to enable the I2C6 mux routing.
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*/
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power_ungate_partition(POWER_PARTID_SOR);
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enable_sor_periphs();
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remove_clamps(POWER_PARTID_SOR);
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unreset_sor_periphs();
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/* Host1X needs a valid clock source so DPAUX can be accessed */
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clock_configure_source(host1x, PLLP, 204000);
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/* Now we can write the I2C6 mux in DPAUX */
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write32(I2C6_PADCTL, (void *)DPAUX_HYBRID_PADCTL);
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}
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