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Angel Pons 65ddbb720b mb/asus/p8h61-m_pro: Add new mainboard
Tested with GRUB 2.02 as a payload, booting Arch Linux as
well as Debian. This code is based on the output of autoport
as well as other mainboards supported in coreboot already.

Working:
 - Serial port I/O
 - S3 suspend/resume. Untested with SeaBIOS since it failed
   to resume on a similar board. It is likely to be due to
   low memory corruption, but I have not worked on it.
 - USB ports and headers
 - USB3 ports attached to the ASM1042 controller. SeaBIOS can
   boot from them, and it is likely GRUB can detect devices on
   those ports as well. The chip has a small SPI flash nearby,
   which seems to hold an Option ROM.
 - Gigabit Ethernet
 - Integrated graphics (libgfxinit)
 - VGA BIOS for integrated graphics init
 - PCIe x16 graphics
 - PCIe x1
 - SATA controller
 - Hardware Monitor
 - Fan Control (fancontrol on linux works well)
 - Native raminit
 - flashrom, using the internal programmer. Tested with coreboot,
   as well as with the vendor firmware.
 - NVRAM settings. Only debug_level has been tested.

Untested:
 - DVI port. It can detect a "fake" display, that is, an
   EEPROM connected to the DVI port. Thus, gma-mainboard.ads
   has been setup accordingly.
 - PS/2 port.
 - Audio: Only rear output (green) has been tested.
 - EHCI debug.
 - Parallel port header.
 - Non-Linux OSes
 - ACPI thermal zone and fan control (probably not working)

Not working:
 - Booting from devices attached to the ASM1061 controller.
   Devices on ports work fine once Linux has loaded.
 - Any SATA devices with Tianocore (payload issue)

Change-Id: I7e89ebe43a2e1ff0308f4876e98bbf2f5a0d85f2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/26419
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-23 22:26:22 +00:00
3rdparty 3rdparty/libgfxinit: Update submodule pointer 2018-06-08 03:27:23 +00:00
Documentation Documentation: Add cavium SoC and mainboard 2018-06-19 18:09:04 +00:00
configs configs: add PC Engines apu2 sample configuration 2018-05-19 16:55:56 +00:00
payloads libpayload: cheza - fix config for chromium chroot build 2018-06-22 13:11:06 +00:00
src mb/asus/p8h61-m_pro: Add new mainboard 2018-06-23 22:26:22 +00:00
util cbfstool/fit.c: Fix for older CPUs without total_size in mcu_header 2018-06-22 09:20:22 +00:00
.checkpatch.conf .checkpatch.conf: Ignore CORRUPTED_PATCH lint 2017-10-29 10:11:58 +00:00
.clang-format clang-format: Update .clang-format to be compliant with linux kernel coding style 2018-04-23 09:26:08 +00:00
.gitignore Documentation: Add support for building with Sphinx 2018-04-26 12:25:03 +00:00
.gitmodules Set up 3rdparty/libgfxinit 2016-10-29 01:35:03 +02:00
.gitreview
COPYING
MAINTAINERS MAINTAINERS: change second PC Engines maintainer 2018-03-21 18:25:49 +00:00
Makefile Makefile: Add filelist to help 2018-01-29 15:35:11 +00:00
Makefile.inc Makefile.inc: Skip -fconserve-stack flag if running scan-build 2018-06-07 16:38:08 +00:00
README README: Update requirements 2017-06-27 17:04:32 +00:00
gnat.adc
toolchain.inc Introduce bootblock self-decompression 2018-05-22 02:44:14 +00:00

README

-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------

coreboot is a Free Software project aimed at replacing the proprietary BIOS
(firmware) found in most computers.  coreboot performs a little bit of
hardware initialization and then executes additional boot logic, called a
payload.

With the separation of hardware initialization and later boot logic,
coreboot can scale from specialized applications that run directly
firmware, run operating systems in flash, load custom
bootloaders, or implement firmware standards, like PC BIOS services or
UEFI. This allows for systems to only include the features necessary
in the target application, reducing the amount of code and flash space
required.

coreboot was formerly known as LinuxBIOS.


Payloads
--------

After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.


Supported Hardware
------------------

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

 * https://www.coreboot.org/Supported_Motherboards
 * https://www.coreboot.org/Supported_Chipsets_and_Devices


Build Requirements
------------------

 * make
 * gcc / g++
   Because Linux distribution compilers tend to use lots of patches. coreboot
   does lots of "unusual" things in its build system, some of which break due
   to those patches, sometimes by gcc aborting, sometimes - and that's worse -
   by generating broken object code.
   Two options: use our toolchain (eg. make crosstools-i386) or enable the
   ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this
   case).
 * iasl (for targets with ACPI support)
 * pkg-config
 * libssl-dev (openssl)

Optional:

 * doxygen (for generating/viewing documentation)
 * gdb (for better debugging facilities on some targets)
 * ncurses (for 'make menuconfig' and 'make nconfig')
 * flex and bison (for regenerating parsers)


Building coreboot
-----------------

Please consult https://www.coreboot.org/Build_HOWTO for details.


Testing coreboot Without Modifying Your Hardware
------------------------------------------------

If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.


Website and Mailing List
------------------------

Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:

  https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

  https://www.coreboot.org/Mailinglist


Copyright and License
---------------------

The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.