coreboot-kgpe-d16/src/southbridge/intel/i3100
Ed Swierk 1149a3692f Tidy up identifiers, per Uwe's suggestion. Trivial.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Ed Swierk <eswierk@arastra.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3563 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-03 23:32:30 +00:00
..
chip.h Here is an updated patch addressing most of Uwe's and Peter's 2008-03-16 23:34:10 +00:00
Config.lb Here is an updated patch addressing most of Uwe's and Peter's 2008-03-16 23:34:10 +00:00
i3100.c Setting an integrated southbridge device (like SATA or USB2.0) to 2008-04-01 17:14:57 +00:00
i3100.h Here is an updated patch addressing most of Uwe's and Peter's 2008-03-16 23:34:10 +00:00
i3100_early_lpc.c By default, the Intel 3100 LPC interface enables only I/O range 0x3f8 2008-04-30 18:29:35 +00:00
i3100_early_smbus.c The early init code of several Intel southbridge chipsets calls 2008-04-01 02:36:59 +00:00
i3100_ehci.c This patch modifies the Intel 3100 southbridge code to recognize the 2008-08-25 14:45:00 +00:00
i3100_lpc.c This patch modifies the Intel 3100 southbridge code to recognize the 2008-08-25 14:45:00 +00:00
i3100_pci.c Here is an updated patch addressing most of Uwe's and Peter's 2008-03-16 23:34:10 +00:00
i3100_reset.c Here is an updated patch addressing most of Uwe's and Peter's 2008-03-16 23:34:10 +00:00
i3100_sata.c Tidy up identifiers, per Uwe's suggestion. Trivial. 2008-09-03 23:32:30 +00:00
i3100_smbus.c This patch modifies the Intel 3100 southbridge code to recognize the 2008-08-25 14:45:00 +00:00
i3100_smbus.h Here is an updated patch addressing most of Uwe's and Peter's 2008-03-16 23:34:10 +00:00
i3100_uhci.c This patch adds PCI device IDs for the Intel EP80579 Integrated Processor, 2008-08-25 17:02:09 +00:00