0867062412
It's basically done with the following script and some manual fixup:
VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC`
for VAR in $VARS; do
find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \;
done
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
81 lines
2 KiB
Text
81 lines
2 KiB
Text
# Config file for Embedded Planet EP405PC board
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# This will make a target directory of ./ep405pc
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target ep405pc
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mainboard embeddedplanet/ep405pc
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romimage "normal"
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## Enable PPC405 instructions
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option CONFIG_CPU_OPT="-mcpu=405"
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## use a cross compiler
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#option CONFIG_CROSS_COMPILE="powerpc-ibm-eabi-"
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## Use stage 1 initialization code
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option CONFIG_USE_INIT=1
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## Use chip configuration
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option CONFIG_CHIP_CONFIGURE=1
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## We don't use compressed image
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option CONFIG_COMPRESS=0
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## Turn off POST codes
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option CONFIG_NO_POST=1
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## Enable serial console
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option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
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option CONFIG_CONSOLE_SERIAL8250=1
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# Divisor of 69 == 9600 baud due to weird clocking
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option CONFIG_TTYS0_DIV=69
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option CONFIG_TTYS0_BAUD=9600
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## Boot linux from IDE
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option CONFIG_IDE=1
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option CONFIG_FS_PAYLOAD=1
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option CONFIG_FS_EXT2=1
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option CONFIG_FS_ISO9660=1
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option CONFIG_FS_FAT=1
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option CONFIG_AUTOBOOT_CMDLINE="hda1:/vmlinuz"
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option CONFIG_ROM_SIZE=1024*1024
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## Board has fixed size RAM
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option CONFIG_EMBEDDED_RAM_SIZE=64*1024*1024
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## Coreboot C code runs at this location in RAM
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option CONFIG_RAMBASE=0x00100000
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##
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## Use a 64K stack
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##
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option CONFIG_STACK_SIZE=0x10000
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##
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## Use a 64K heap
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##
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option CONFIG_HEAP_SIZE=0x10000
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##
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## System clock
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##
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option CONFIG_SYS_CLK_FREQ=33
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##
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option CONFIG_ROMBASE=0xfff00000
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## Reset vector address
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option CONFIG_RESET=0xfffffffc
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## Exception vectors
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option CONFIG_EXCEPTION_VECTORS=CONFIG_ROMBASE+0x100
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## coreboot ROM start address
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option CONFIG_ROMSTART=0xfff03000
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## coreboot C code runs at this location in RAM
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option CONFIG_RAMBASE=0x00100000
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end
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buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal"
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