Karthikeyan Ramasubramanian 674b07247e soc/amd/common/block/apob_cache: Add support for RECOVERY_MRC_CACHE ... If a mainboard has RECOVERY_MRC_CACHE and the recovery mode is enabled, then use APOB data from that section and make any updates to that section. Otherwise continue to use DEFAULT_MRC_CACHE section. BUG=b:270569389 TEST=Build and boot to OS in Skyrim. When in normal mode, DEFAULT_MRC_CACHE is used. Normal Mode Boot1: ------------------ [DEBUG] FMAP: area RW_MRC_CACHE found @ 0 (122880 bytes) [INFO ] APOB RAM hash differs from flash [SPEW ] Copy APOB from RAM 0x02001000/0x1db18 to flash 0x0/0x1e000 [DEBUG] FMAP: area RW_MRC_CACHE found @ 0 (122880 bytes) [DEBUG] SF: Successfully erased 122880 bytes @ 0x0 [INFO ] Updated APOB in flash Normal Mode Boot2: ----------------- [DEBUG] FMAP: area RW_MRC_CACHE found @ 0 (122880 bytes) [DEBUG] APOB hash matches flash When the device is in recovery mode, RECOVERY_MRC_CACHE is used. Recovery Mode Boot1: -------------------- [DEBUG] FMAP: area RECOVERY_MRC_CACHE found @ 650000 (122880 bytes) [INFO ] APOB RAM hash differs from flash [SPEW ] Copy APOB from RAM 0x02001000/0x1db18 to flash 0x650000/0x1e000 [DEBUG] FMAP: area RECOVERY_MRC_CACHE found @ 650000 (122880 bytes) [DEBUG] SF: Successfully erased 122880 bytes @ 0x650000 [INFO ] Updated APOB in flash Recovery Mode Boot2: -------------------- [DEBUG] FMAP: area RECOVERY_MRC_CACHE found @ 650000 (122880 bytes) [DEBUG] APOB hash matches flash Switch from Recovery Mode to Normal Mode: ----------------------------------------- [DEBUG] FMAP: area RW_MRC_CACHE found @ 0 (122880 bytes) [DEBUG] APOB hash matches flash Switch from Normal Mode to Recovery Mode: ----------------------------------------- [DEBUG] FMAP: area RECOVERY_MRC_CACHE found @ 650000 (122880 bytes) [DEBUG] APOB hash matches flash Change-Id: I93f357e407c98b6e5fca495f4f779fad54a3430f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>		2023-02-27 19:12:03 +00:00
..
amd	soc/amd/common/block/apob_cache: Add support for RECOVERY_MRC_CACHE	2023-02-27 19:12:03 +00:00
cavium	treewide: Remove duplicated include <device/pci.h>	2023-02-01 03:03:34 +00:00
example/min86	soc: Add SPDX license headers to Makefiles	2022-10-31 03:27:13 +00:00
intel	soc/intel/elkhartlake/romstage/fsp_params.c: separate debug params	2023-02-27 16:45:36 +00:00
mediatek	soc/mediatek: Add "DRAM" to Kconfig MEDIATEK_BLOB_FAST_INIT name	2023-02-23 12:14:47 +00:00
nvidia	treewide: stop calling custom TPM log "TCPA"	2023-01-11 16:00:55 +00:00
qualcomm	Revert "soc/qualcomm: Increase SPI frequency to 75 MHz"	2023-02-24 19:28:24 +00:00
rockchip	cbmem_top_chipset: Change the return value to uintptr_t	2022-11-18 16:00:45 +00:00
samsung	treewide: Fix old-style declarations	2023-01-17 04:23:49 +00:00
sifive/fu540	cbmem_top_chipset: Change the return value to uintptr_t	2022-11-18 16:00:45 +00:00
ti	src/soc/ti: Remove unnecessary space after casts	2022-11-22 13:42:28 +00:00
ucb/riscv	cbmem_top_chipset: Change the return value to uintptr_t	2022-11-18 16:00:45 +00:00