coreboot-kgpe-d16/src
Aaron Durbin 67633a558a baytrail: use MCRX in iosf access functions
While most registers accesses don't need the use of the MCRX
register (upper 24 bits of address) the MCRX register should
be protected. The reference code could be doing accesses to
registers that initialized the MCRX register. Thus, any access
after that should ensure the MCRX register is initialized
appropriately.

BUG=None
BRANCH=None
TEST=Verified assembly output. Also, built and booted through
     depthcharge.

Change-Id: I4d6cfbe6bb1666790c69778b8f2c8baeaf015264
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174643
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4909
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-27 06:12:25 +01:00
..
arch CAR_GLOBAL: enforce compiler to check if _start != _end 2014-02-24 13:54:02 +01:00
console usbdebug: Unify console API 2014-02-20 23:29:12 +01:00
cpu Remove CACHE_ROM. 2014-02-25 00:57:35 +01:00
device device: Do not show "framebuffer graphics resolution" with native init. 2014-02-22 09:07:53 +01:00
drivers usbdebug: Unify console API 2014-02-20 23:29:12 +01:00
ec chromeec: allow override of i8042 interrupt 2014-01-30 05:36:33 +01:00
include Remove CACHE_ROM. 2014-02-25 00:57:35 +01:00
lib Kill ALT_CBFS_LOAD_PAYLOAD 2014-02-25 20:03:49 +01:00
mainboard Remove CACHE_ROM. 2014-02-25 00:57:35 +01:00
northbridge Remove CACHE_ROM. 2014-02-25 00:57:35 +01:00
soc baytrail: use MCRX in iosf access functions 2014-02-27 06:12:25 +01:00
southbridge lynxpoint: Kill alternative cbfs_load_payload. 2014-02-25 20:03:34 +01:00
superio superio/fintek: Document Fintek F71869AD code. 2014-02-13 17:14:20 +01:00
vendorcode coreboot: infrastructure for different ramstage loaders 2014-02-15 18:39:29 +01:00
Kconfig Kill ALT_CBFS_LOAD_PAYLOAD 2014-02-25 20:03:49 +01:00