Subrata Banik efbfdd2d60 soc/intel/skylake: Move PCR DMI programming into bootblock ... As per PCH BWG 2.5.16, set up LPC IO Enables PCR[DMI] + 2774h bit [15:0] to the same value program in LPC PCI offset 82h. Also this cycle decoding is only allowed to set when SRLOCK is not set. Hence move the required programming from lpc.c to pch.c. Also only enable COM port ranges if CONFIG_DRIVERS_UART_8250IO Kconfig is selected. Change-Id: Ie706735492a450baa653d8a8bb74c6e42f5150b8 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2018-03-09 21:40:32 +00:00
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apollolake	src/soc: Fix various typos	2018-02-20 23:17:39 +00:00
baytrail	security/tpm: Change TPM naming for different layers.	2018-01-18 01:45:35 +00:00
braswell	soc/intel/braswell: add resource allocation for LPE BAR1	2018-03-08 18:19:28 +00:00
broadwell	soc/intel/broadwell: Generate ACPI DMAR table	2018-03-01 16:10:25 +00:00
cannonlake	soc/intel/cannonlake: Clear EMMC timeout register	2018-02-22 09:59:03 +00:00
common	soc/intel/common: Enable decoding of the COMB range to LPC based on Kconfig	2018-03-09 21:40:09 +00:00
denverton_ns	soc/intel/denverton_ns: Update UART legacy mode to keep FSP traces	2018-03-09 12:57:54 +00:00
fsp_baytrail	soc/intel/fsp_baytrail: remove nvm headers and code	2017-12-17 18:29:08 +00:00
fsp_broadwell_de	Constify struct cpu_device_id instances	2017-11-23 05:00:17 +00:00
quark	drivers/spi: support cmd opcode deduction for spi_crop_chunk()	2018-01-30 05:37:47 +00:00
skylake	soc/intel/skylake: Move PCR DMI programming into bootblock	2018-03-09 21:40:32 +00:00
Kconfig	soc: Add Kconfig for each soc vendor	2017-10-23 17:18:32 +00:00