coreboot-kgpe-d16/src/southbridge/amd
Felix Held 70d1c723f7 sb/amd/pi/hudson: remove unused Bolton PI FCH code
There is no nb/amd/pi northbridge left in coreboot that could be paired
with the Bolton FCH, since the remaining nb/amd/pi northbridges all use
an integrated FCH (Avalon on Mullins and Kern on Carrizo) while Bolton
is a discrete FCH. I ran into this when verifying if the common soc/amd
GPIO functionality that gets added by selecting
SOC_AMD_COMMON_BLOCK_BANKED_GPIOS is valid for all chips selecting it
and that code isn't valid for Bolton that uses the old GPIO 100
interface.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iffe876bee96e42645e1be10730b78959b1c06d59
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52222
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-11 21:06:29 +00:00
..
agesa sb/amd/agesa/hudson/lpc: Remove space between function and signature 2021-02-25 10:04:01 +00:00
cimx ACPI: Use common OperationRegion for PCI_MMCONF 2021-02-20 21:38:54 +00:00
common sb/amd/pi/hudson: remove unused Bolton PI FCH code 2021-04-11 21:06:29 +00:00
pi sb/amd/pi/hudson: remove unused Bolton PI FCH code 2021-04-11 21:06:29 +00:00