a050817ce5
This moves the sandybridge both smm setup and smihandler code to a common place. Tested on Thinkpad X220, still boots, resume to and from S3 is fine so smihandler is still working fine. Change-Id: I28e2e6ad1e95a9e14462a456726a144ccdc63ec9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
37 lines
969 B
Text
37 lines
969 B
Text
config SOUTHBRIDGE_INTEL_COMMON
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def_bool n
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config SOUTHBRIDGE_INTEL_COMMON_GPIO
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def_bool n
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config SOUTHBRIDGE_INTEL_COMMON_SMBUS
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def_bool n
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select HAVE_DEBUG_SMBUS
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config SOUTHBRIDGE_INTEL_COMMON_SPI
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def_bool n
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select SPI_FLASH
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config SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN
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def_bool n
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config SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
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def_bool n
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select SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN
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config HAVE_INTEL_CHIPSET_LOCKDOWN
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def_bool n
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config SOUTHBRIDGE_INTEL_COMMON_SMM
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def_bool n
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config INTEL_CHIPSET_LOCKDOWN
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depends on HAVE_INTEL_CHIPSET_LOCKDOWN && HAVE_SMI_HANDLER && !CHROMEOS
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#ChromeOS's payload seems to handle finalization on its on.
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bool "Lock down chipset in coreboot"
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default y
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help
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Some registers within host bridge on particular chipsets should be
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locked down on each normal boot path (done by either coreboot or payload)
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and S3 resume (always done by coreboot). Select this to let coreboot
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to do this on normal boot path.
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