3b7668325b
Change-Id: I2ea07cdeb8fc70dbf516831f4da5949fef136b37 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
44 lines
1.6 KiB
Makefile
44 lines
1.6 KiB
Makefile
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2008-2009 coresystems GmbH
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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# CONFIG_HAVE_INTEL_FIRMWARE protects doing anything to the build.
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subdirs-y += firmware
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ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y)
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romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += usb_debug.c
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ramstage-$(CONFIG_USBDEBUG) += usb_debug.c
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romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c
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ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c
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smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c
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romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c
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ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c
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romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c
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postcar-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c
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ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c
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ifeq ($(CONFIG_SPI_FLASH_SMM),y)
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smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c
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endif
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ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN) += acpi_pirq_gen.c
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ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ) += rcba_pirq.c
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ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM) += pmutil.c smi.c
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smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM) += pmutil.c smihandler.c
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endif
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