Felix Held 9ef72ca7db mb/google/kahlee: move SMI/SCI GPIO setup to ramstage ... SMIs and SCIs aren't used before ramstage or the OS, so there should be no need to already set them up in romstage. Not using this GPIO configuration functionality allows untangling the GPIO and smi_util code and only linking smi_util in ramstage in follow-up patches. In romstage the pins get initialized as inputs with pull-up, so that at least that part still matches the configuration before this patch. BUG=b:175386410 Change-Id: I733bb91ef60dc66093781a376a2e9837f5209671 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48608 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>		2020-12-13 22:20:13 +00:00
..
bootblock
spd
variants	mb/google/kahlee: move SMI/SCI GPIO setup to ramstage	2020-12-13 22:20:13 +00:00
BiosCallOuts.c
board_info.txt
chromeos.c
dsdt.asl	mb/*/*/dsdt.asl: Drop useless comments in DefinitionBlock()	2020-10-13 18:27:23 +00:00
ec.c
irq_tables.c
Kconfig	treewide: rename GENERIC_SPD_BIN to HAVE_SPD_BIN_IN_CBFS	2020-09-23 09:00:47 +00:00
Kconfig.name
mainboard.c	soc/amd: factor out common SMI/SCI enums and function prototypes	2020-12-02 21:33:14 +00:00
Makefile.inc
mptable.c
OemCustomize.c
romstage.c
smihandler.c