c01a9ab562
All ARM architecture boards are supposed to have a TTB region for their page tables. ARM systems cannot use the data cache without enabling paging, so it is imperative to do that as soon as possible. They will also fault on unaligned accesses when not using the cache, which breaks assumptions in CBFS code. Unfortunately, we have some old boards in various stages of disrepair in the tree that don't always follow these sorts of standard conventions. It's not clear whether they actually boot anymore and if anyone still has the respective hardware available to maintain them. I cannot really fix and test them right now, but we should at least create a fake TTB section for them so that common architecture code may make the correct assumptions about which regions exist. Change-Id: I51aa259fbb7a9c0ade72db905b1762c1c721f387 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/25903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> |
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