c02b4fc9db
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
199 lines
6.3 KiB
C
199 lines
6.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <arch/io.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/mtrr.h>
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#include "rs690.h"
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/*****************************************
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* Compliant with CIM_33's ATINB_MiscClockCtrl
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*****************************************/
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void static rs690_config_misc_clk(device_t nb_dev)
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{
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u32 reg;
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u16 word;
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/* u8 byte; */
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struct bus pbus; /* fake bus for dev0 fun1 */
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reg = pci_read_config32(nb_dev, 0x4c);
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reg |= 1 << 0;
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pci_write_config32(nb_dev, 0x4c, reg);
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word = pci_cf8_conf1.read16(&pbus, 0, 1, 0xf8);
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word &= 0xf00;
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pci_cf8_conf1.write16(&pbus, 0, 1, 0xf8, word);
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word = pci_cf8_conf1.read16(&pbus, 0, 1, 0xe8);
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word &= ~((1 << 12) | (1 << 13) | (1 << 14));
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word |= 1 << 13;
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pci_cf8_conf1.write16(&pbus, 0, 1, 0xe8, word);
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reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x94);
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reg &= ~((1 << 16) | (1 << 24) | (1 << 28));
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pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg);
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reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x8c);
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reg &= ~((1 << 13) | (1 << 14) | (1 << 24) | (1 << 25));
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reg |= 1 << 13;
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pci_cf8_conf1.write32(&pbus, 0, 1, 0x8c, reg);
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reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc);
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reg |= 1 << 24;
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pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg);
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reg = nbmc_read_index(nb_dev, 0x7a);
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reg &= ~0x3f;
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reg |= 1 << 2;
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reg &= ~(1 << 6);
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set_htiu_enable_bits(nb_dev, 0x05, 1 << 11, 1 << 11);
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nbmc_write_index(nb_dev, 0x7a, reg);
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/* Powering Down efuse and strap block clocks after boot-up. GFX Mode. */
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reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc);
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reg &= ~(1 << 23);
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reg |= 1 << 24;
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pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg);
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#if 0
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/* Powerdown reference clock to graphics core PLL in northbridge only mode */
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reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x8c);
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reg |= 1 << 21;
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pci_cf8_conf1.write32(&pbus, 0, 1, 0x8c, reg);
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/* Powering Down efuse and strap block clocks after boot-up. NB Only Mode. */
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reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc);
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reg |= (1 << 23) | (1 << 24);
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pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg);
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/* Powerdown clock to memory controller in northbridge only mode */
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byte = pci_cf8_conf1.read8(&pbus, 0, 1, 0xe4);
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byte |= 1 << 0;
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pci_cf8_conf1.write8(&pbus, 0, 1, 0xe4, reg);
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/* CLKCFG:0xE8 Bit[17] = 0x1 Powerdown clock to IOC GFX block in no external graphics mode */
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/* TODO: */
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#endif
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reg = pci_read_config32(nb_dev, 0x4c);
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reg &= ~(1 << 0);
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pci_write_config32(nb_dev, 0x4c, reg);
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set_htiu_enable_bits(nb_dev, 0x05, 7 << 8, 7 << 8);
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}
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u32 get_vid_did(device_t dev)
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{
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return pci_read_config32(dev, 0);
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}
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/***********************************************
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* 0:00.0 NBCFG :
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* 0:00.1 CLK : bit 0 of nb_cfg 0x4c : 0 - disable, default
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* 0:01.0 P2P Internal:
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* 0:02.0 P2P : bit 2 of nbmiscind 0x0c : 0 - enable, default + 32 * 2
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* 0:03.0 P2P : bit 3 of nbmiscind 0x0c : 0 - enable, default + 32 * 2
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* 0:04.0 P2P : bit 4 of nbmiscind 0x0c : 0 - enable, default + 32 * 2
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* 0:05.0 P2P : bit 5 of nbmiscind 0x0c : 0 - enable, default + 32 * 2
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* 0:06.0 P2P : bit 6 of nbmiscind 0x0c : 0 - enable, default + 32 * 2
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* 0:07.0 P2P : bit 7 of nbmiscind 0x0c : 0 - enable, default + 32 * 2
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* 0:08.0 NB2SB : bit 6 of nbmiscind 0x00 : 0 - disable, default + 32 * 1
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* case 0 will be called twice, one is by cpu in hypertransport.c line458,
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* the other is by rs690.
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***********************************************/
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void rs690_enable(device_t dev)
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{
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device_t nb_dev = 0, sb_dev = 0;
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int dev_ind;
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printk(BIOS_INFO, "rs690_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev));
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nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
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if (!nb_dev) {
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die("rs690_enable: CAN NOT FIND RS690 DEVICE, HALT!\n");
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/* NOT REACHED */
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}
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/* sb_dev (dev 8) is a bridge that links to southbridge. */
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sb_dev = dev_find_slot(0, PCI_DEVFN(8, 0));
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if (!sb_dev) {
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die("rs690_enable: CAN NOT FIND SB bridge, HALT!\n");
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/* NOT REACHED */
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}
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dev_ind = dev->path.pci.devfn >> 3;
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switch (dev_ind) {
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case 0: /* bus0, dev0, fun0; */
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printk(BIOS_INFO, "Bus-0, Dev-0, Fun-0.\n");
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enable_pcie_bar3(nb_dev); /* PCIEMiscInit */
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config_gpp_core(nb_dev, sb_dev);
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rs690_gpp_sb_init(nb_dev, sb_dev, 8);
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/* set SB payload size: 64byte */
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set_pcie_enable_bits(nb_dev, 0x10 | PCIE_CORE_INDEX_GPPSB, 3 << 11, 2 << 11);
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/* Bus0Dev0Fun1Clock control init, we have to do it here, for dev0 Fun1 doesn't have a vendor or device ID */
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rs690_config_misc_clk(nb_dev);
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break;
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case 1: /* bus0, dev1 */
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printk(BIOS_INFO, "Bus-0, Dev-1, Fun-0.\n");
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break;
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case 2: /* bus0, dev2,3, two GFX */
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case 3:
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printk(BIOS_INFO, "Bus-0, Dev-2,3, Fun-0. enable=%d\n", dev->enabled);
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set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind,
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(dev->enabled ? 0 : 1) << dev_ind);
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if (dev->enabled)
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rs690_gfx_init(nb_dev, dev, dev_ind);
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break;
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case 4: /* bus0, dev4-7, four GPP */
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case 5:
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case 6:
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case 7:
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printk(BIOS_INFO, "Bus-0, Dev-4,5,6,7, Fun-0. enable=%d\n",
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dev->enabled);
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set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind,
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(dev->enabled ? 0 : 1) << dev_ind);
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if (dev->enabled)
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rs690_gpp_sb_init(nb_dev, dev, dev_ind);
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break;
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case 8: /* bus0, dev8, SB */
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printk(BIOS_INFO, "Bus-0, Dev-8, Fun-0. enable=%d\n", dev->enabled);
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set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6,
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(dev->enabled ? 1 : 0) << 6);
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if (dev->enabled)
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rs690_gpp_sb_init(nb_dev, dev, dev_ind);
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disable_pcie_bar3(nb_dev);
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break;
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default:
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printk(BIOS_DEBUG, "unknown dev: %s\n", dev_path(dev));
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}
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}
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struct chip_operations southbridge_amd_rs690_ops = {
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CHIP_NAME("ATI RS690")
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.enable_dev = rs690_enable,
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};
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