6a503b6a0f
This patch makes pre-RAM serial init more generic, particularly for platforms which do not necessarily need cache-as-RAM in order to use the serial console and do not have a standard 8250 serial port. This adds a Kconfig variable to set romstage-* for very early serial console init. The current method assumes that cache-as-RAM should enable this, so to maintain compatibility selecting CACHE_AS_RAM will also select EARLY_SERIAL_CONSOLE. The UART code structure needs some rework, but the use of ROMCC, romstage, and then ramstage makes things complex. uart.h now includes all .h files for all uarts. All 2 of them. This is actually a simplifying change. Change-Id: I089e7af633c227baf3c06c685f005e9d0e4b38ce Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2086 Tested-by: build bot (Jenkins)
72 lines
1.8 KiB
C
72 lines
1.8 KiB
C
/*
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* (C) Copyright 2012 The ChromiumOS Authors
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* (C) Copyright 2009 Samsung Electronics
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* Minkyu Kang <mk7.kang@samsung.com>
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* Heungjun Kim <riverful.kim@samsung.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* This file is based off of arch/arm/include/asm/arch-exynos5/uart.h
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* from u-boot.
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*/
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#ifndef __EXYNOS5_UART_H_
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#define __EXYNOS5_UART_H_
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#include <types.h>
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/* FIXME: should these move into a Kconfig file? */
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#define EXYNOS5_UART0_BASE 0x12c00000
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#define EXYNOS5_UART1_BASE 0x12c10000
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#define EXYNOS5_UART2_BASE 0x12c20000
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#define EXYNOS5_UART3_BASE 0x12c30000
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#define EXYNOS5_ISP_UART_BASE 0x13190000
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#if 0
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/* baudrate rest value */
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union br_rest {
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unsigned short slot; /* udivslot */
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unsigned char value; /* ufracval */
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};
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#endif
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struct s5p_uart {
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uint32_t ulcon;
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uint32_t ucon;
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uint32_t ufcon;
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uint32_t umcon;
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uint32_t utrstat;
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uint32_t uerstat;
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uint32_t ufstat;
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uint32_t umstat;
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uint8_t utxh;
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uint8_t res1[3];
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uint8_t urxh;
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uint8_t res2[3];
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uint32_t ubrdiv;
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uint32_t ufracval;
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uint32_t uintp;
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uint32_t uints;
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uint32_t uintm;
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};
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static inline int s5p_uart_divslot(void)
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{
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return 0;
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}
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void uart_init(void);
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#endif
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