Arthur Heymans 6a8cde4927 soc/intel/cpu: Select NO_FIXED_XIP_ROM_SIZE ... The cache as ram code will use one form of a non-eviction mode. Change-Id: I418eb48434aa3da3bf5ca65315bb8c9077523966 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>		2020-03-04 16:20:28 +00:00
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apollolake	soc/intel/cpu: Select NO_FIXED_XIP_ROM_SIZE	2020-03-04 16:20:28 +00:00
baytrail	src: capitalize 'PCIe'	2020-03-04 15:43:30 +00:00
braswell	src: capitalize 'PCIe'	2020-03-04 15:43:30 +00:00
broadwell	src: capitalize 'PCIe'	2020-03-04 15:43:30 +00:00
cannonlake	soc/intel/cpu: Select NO_FIXED_XIP_ROM_SIZE	2020-03-04 16:20:28 +00:00
common	soc/intel/cpu: Select NO_FIXED_XIP_ROM_SIZE	2020-03-04 16:20:28 +00:00
denverton_ns	src: capitalize 'PCIe'	2020-03-04 15:43:30 +00:00
icelake	src: capitalize 'PCIe'	2020-03-04 15:43:30 +00:00
quark	soc/intel: Add get_pmbase	2020-02-04 18:54:01 +00:00
skylake	soc/intel/cpu: Select NO_FIXED_XIP_ROM_SIZE	2020-03-04 16:20:28 +00:00
tigerlake	src: capitalize 'PCIe'	2020-03-04 15:43:30 +00:00
Kconfig	soc/intel/Kconfig: Load Tiger Lake SOC Kconfig	2019-12-11 11:37:45 +00:00