91 lines
2.7 KiB
C
91 lines
2.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* cache.c: Cache Maintenance Instructions
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* Reference: ARM Architecture Reference Manual, ARMv8-A edition
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*/
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#include <stdint.h>
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#include <arch/lib_helpers.h>
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void dccisw(uint64_t cisw)
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{
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__asm__ __volatile__("dc cisw, %0\n\t" : : "r" (cisw) :"memory");
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}
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void dccivac(uint64_t civac)
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{
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__asm__ __volatile__("dc civac, %0\n\t" : : "r" (civac) :"memory");
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}
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void dccsw(uint64_t csw)
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{
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__asm__ __volatile__("dc csw, %0\n\t" : : "r" (csw) :"memory");
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}
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void dccvac(uint64_t cvac)
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{
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__asm__ __volatile__("dc cvac, %0\n\t" : : "r" (cvac) :"memory");
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}
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void dccvau(uint64_t cvau)
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{
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__asm__ __volatile__("dc cvau, %0\n\t" : : "r" (cvau) :"memory");
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}
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void dcisw(uint64_t isw)
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{
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__asm__ __volatile__("dc isw, %0\n\t" : : "r" (isw) :"memory");
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}
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void dcivac(uint64_t ivac)
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{
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__asm__ __volatile__("dc ivac, %0\n\t" : : "r" (ivac) :"memory");
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}
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void dczva(uint64_t zva)
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{
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__asm__ __volatile__("dc zva, %0\n\t" : : "r" (zva) :"memory");
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}
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void iciallu(void)
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{
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__asm__ __volatile__("ic iallu\n\t" : : :"memory");
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}
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void icialluis(void)
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{
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__asm__ __volatile__("ic ialluis\n\t" : : :"memory");
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}
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void icivau(uint64_t ivau)
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{
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__asm__ __volatile__("ic ivau, %0\n\t" : : "r" (ivau) :"memory");
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}
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