6aa9f1f0eb
The bus clock speed is needed when building ACPI P-state tables so extract that function and have the value be saved in pattrs. The various IACORE values are also needed, but rather than have the ACPI code to the bit manipulation have the pattrs store an array of the possible values for it to use directly. BUG=chrome-os-partner:23505 BRANCH=none TEST=build and boot on rambi Change-Id: I5ac06ccf66e9109186dd01342dbb6ccdd334ca69 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176140 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4953 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
84 lines
2 KiB
C
84 lines
2 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <stdint.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/tsc.h>
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#include <baytrail/msr.h>
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unsigned bus_freq_khz(void)
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{
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msr_t clk_info = rdmsr(MSR_BSEL_CR_OVERCLOCK_CONTROL);
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switch (clk_info.lo & 0x3) {
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case 0:
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return 83333;
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case 1:
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return 100000;
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case 2:
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return 133333;
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case 3:
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return 116666;
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default:
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return 0;
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}
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}
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unsigned long tsc_freq_mhz(void)
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{
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msr_t platform_info;
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unsigned bclk_khz = bus_freq_khz();
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if (!bclk_khz)
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return 0;
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platform_info = rdmsr(MSR_PLATFORM_INFO);
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return (bclk_khz * ((platform_info.lo >> 8) & 0xff)) / 1000;
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}
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#if !defined(__SMM__)
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#if !defined(__PRE_RAM__)
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#include <baytrail/ramstage.h>
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#else
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#include <baytrail/romstage.h>
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#endif
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void set_max_freq(void)
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{
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msr_t perf_ctl;
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msr_t msr;
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/* Enable speed step. */
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msr = rdmsr(MSR_IA32_MISC_ENABLES);
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msr.lo |= (1 << 16);
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wrmsr(MSR_IA32_MISC_ENABLES, msr);
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/* Set guranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of
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* the PERF_CTL. */
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msr = rdmsr(MSR_IACORE_RATIOS);
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perf_ctl.lo = (msr.lo & 0x3f0000) >> 8;
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/* Set guranteed vid [21:16] from IACORE_VIDS to bits [7:0] of
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* the PERF_CTL. */
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msr = rdmsr(MSR_IACORE_VIDS);
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perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16;
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perf_ctl.hi = 0;
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wrmsr(MSR_IA32_PERF_CTL, perf_ctl);
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}
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#endif /* __SMM__ */
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