3129f792f7
This should be able to generate bootable ports for sandy/ivy, possible with minor fixes. Howto is in readme.md Change-Id: Ia126cf0939ef2dc2cdbb7ea100d2b63ea6b02f28 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7131 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
39 lines
1.3 KiB
Go
39 lines
1.3 KiB
Go
package main
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import "fmt"
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type rce823 struct {
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variant string
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}
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func (r rce823) Scan(ctx Context, addr PCIDevData) {
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if addr.Dev == 0 && addr.Func == 0 {
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cur := DevTreeNode{
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Chip: "drivers/ricoh/rce822",
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Comment: "Ricoh cardreader",
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Registers: map[string]string{
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"sdwppol": fmt.Sprintf("%d", (addr.ConfigDump[0xfb]&2)>>1),
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"disable_mask": fmt.Sprintf("0x%x", addr.ConfigDump[0xcb]),
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},
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PCISlots: []PCISlot{
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PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 0}, writeEmpty: false},
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PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 1}, writeEmpty: false},
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PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 2}, writeEmpty: false},
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PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 3}, writeEmpty: false},
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PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 4}, writeEmpty: false},
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PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 5}, writeEmpty: false},
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PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 6}, writeEmpty: false},
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PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 7}, writeEmpty: false},
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},
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}
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PutPCIChip(addr, cur)
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}
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PutPCIDev(addr, "Ricoh SD card reader")
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KconfigBool["DRIVERS_RICOH_RCE822"] = true
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}
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func init() {
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RegisterPCI(0x1180, 0xe822, rce823{})
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RegisterPCI(0x1180, 0xe823, rce823{})
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}
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