coreboot-kgpe-d16/src
Furquan Shaikh 6b19071ffb FUI: Fill in link_m and link_n values
... based on the EDID detailed timing values for
pixel_clock and link_clock.

Two undocumented registers 0x6f040 and 0x6f044 correspond to link_m and link_n
respectively.  Other two undocumented registers 0x6f030 and 0x6f034 correspond
to data_m and data_n respectively.

Calculations are based on the intel_link_compute_m_n from linux kernel.

Currently, the value for 0x6f030 does not come up right with our calculations.
Hence, set to hard-coded value.

Change-Id: I40ff411729d0a61759164c3c1098504973f9cf5e
Reviewed-on: https://gerrit.chromium.org/gerrit/62915
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/4381
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 08:04:10 +01:00
..
arch armv7: Fix dcache_clean_by_mva. 2013-12-12 22:03:01 +01:00
console snprintf: lockless operation 2013-12-07 19:27:53 +01:00
cpu haswell: Update microcode revision 2013-12-21 07:39:04 +01:00
device device/dram/ddr3: Move CRC calculation in a separate function 2013-12-17 19:59:22 +01:00
drivers FUI: Fill in link_m and link_n values 2013-12-21 08:04:10 +01:00
ec ec/lenovo/h8: Enable 3G modem 2013-12-19 08:58:16 +01:00
include FUI: Fill in link_m and link_n values 2013-12-21 08:04:10 +01:00
lib FUI: Fill in link_m and link_n values 2013-12-21 08:04:10 +01:00
mainboard FUI: Fill in link_m and link_n values 2013-12-21 08:04:10 +01:00
northbridge haswell: Add pei_data field for USB routing 2013-12-21 07:39:33 +01:00
southbridge lynxpoint: Avoid any ME device communication in S3 path 2013-12-21 07:38:54 +01:00
superio Correct file permissions. 2013-12-07 00:39:09 +01:00
vendorcode chromeos: Check for recovery reason code in shared data 2013-12-21 07:28:37 +01:00
Kconfig Add GRUB2 payload to build system 2013-11-19 01:07:25 +01:00