7a0b9c5e73
Change-Id: I1ded9fcec9594977b9b9c8d3c105f9998c0ee2bc Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51656 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
78 lines
2.1 KiB
C
78 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <amdblocks/acpimmio.h>
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#include <amdblocks/i2c.h>
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#include <soc/i2c.h>
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#include <soc/iomap.h>
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#include <soc/pci_devs.h>
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#include <soc/southbridge.h>
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#include "chip.h"
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#if ENV_X86
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/* Preferably keep all the I2C controllers operating in a specific mode together. */
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static const struct soc_i2c_ctrlr_info i2c_ctrlr[I2C_CTRLR_COUNT] = {
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{ I2C_MASTER_MODE, 0, "" },
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{ I2C_MASTER_MODE, 0, "" },
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{ I2C_MASTER_MODE, APU_I2C2_BASE, "I2C2" },
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{ I2C_MASTER_MODE, APU_I2C3_BASE, "I2C3" },
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{ I2C_PERIPHERAL_MODE, APU_I2C4_BASE, "I2C4" } /* Can only be used in peripheral mode */
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};
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#else
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static struct soc_i2c_ctrlr_info i2c_ctrlr[I2C_CTRLR_COUNT] = {
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{ I2C_MASTER_MODE, 0, ""},
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{ I2C_MASTER_MODE, 0, "" },
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{ I2C_MASTER_MODE, 0, "" },
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{ I2C_MASTER_MODE, 0, "" },
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{ I2C_PERIPHERAL_MODE, 0, "" },
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};
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void i2c_set_bar(unsigned int bus, uintptr_t bar)
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{
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if (bus >= ARRAY_SIZE(i2c_ctrlr)) {
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printk(BIOS_ERR, "Error: i2c index out of bounds: %u.", bus);
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return;
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}
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i2c_ctrlr[bus].bar = bar;
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}
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#endif
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__weak void mainboard_i2c_override(int bus, uint32_t *pad_settings) { }
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void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg)
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{
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uint32_t pad_ctrl;
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int misc_reg;
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misc_reg = MISC_I2C0_PAD_CTRL + sizeof(uint32_t) * bus;
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pad_ctrl = misc_read32(misc_reg);
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pad_ctrl &= ~I2C_PAD_CTRL_NG_MASK;
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pad_ctrl |= I2C_PAD_CTRL_NG_NORMAL;
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pad_ctrl &= ~I2C_PAD_CTRL_RX_SEL_MASK;
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pad_ctrl |= I2C_PAD_CTRL_RX_SEL_3_3V;
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pad_ctrl &= ~I2C_PAD_CTRL_FALLSLEW_MASK;
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pad_ctrl |= cfg->speed == I2C_SPEED_STANDARD ?
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I2C_PAD_CTRL_FALLSLEW_STD : I2C_PAD_CTRL_FALLSLEW_LOW;
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pad_ctrl |= I2C_PAD_CTRL_FALLSLEW_EN;
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mainboard_i2c_override(bus, &pad_ctrl);
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misc_write32(misc_reg, pad_ctrl);
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}
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const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs)
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{
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*num_ctrlrs = ARRAY_SIZE(i2c_ctrlr);
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return i2c_ctrlr;
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}
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const struct dw_i2c_bus_config *soc_get_i2c_bus_config(size_t *num_buses)
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{
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const struct soc_amd_picasso_config *config = config_of_soc();
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*num_buses = ARRAY_SIZE(config->i2c);
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return config->i2c;
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}
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