6b5bc77c9b
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
118 lines
3.1 KiB
C
118 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
|
|
|
|
#include <bootstate.h>
|
|
#include <cbmem.h>
|
|
#include <console/console.h>
|
|
#include <stdint.h>
|
|
#include <elog.h>
|
|
#include <intelblocks/pmclib.h>
|
|
#include <soc/pci_devs.h>
|
|
#include <soc/pm.h>
|
|
|
|
static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start)
|
|
{
|
|
int i;
|
|
|
|
gpe0_sts &= gpe0_en;
|
|
|
|
for (i = 0; i <= 31; i++) {
|
|
if (gpe0_sts & (1 << i))
|
|
elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start);
|
|
}
|
|
}
|
|
|
|
static void pch_log_wake_source(struct chipset_power_state *ps)
|
|
{
|
|
/* Power Button */
|
|
if (ps->pm1_sts & PWRBTN_STS)
|
|
elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0);
|
|
|
|
/* RTC */
|
|
if (ps->pm1_sts & RTC_STS)
|
|
elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0);
|
|
|
|
/* PCI Express (TODO: determine wake device) */
|
|
if (ps->pm1_sts & PCIEXPWAK_STS)
|
|
elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0);
|
|
|
|
/* PME (TODO: determine wake device) */
|
|
if (ps->gpe0_sts[GPE_STD] & PME_STS)
|
|
elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0);
|
|
|
|
/* Internal PME (TODO: determine wake device) */
|
|
if (ps->gpe0_sts[GPE_STD] & PME_B0_STS)
|
|
elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0);
|
|
|
|
/* SMBUS Wake */
|
|
if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS)
|
|
elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0);
|
|
|
|
/* Log GPIO events in set 1-3 */
|
|
pch_log_gpio_gpe(ps->gpe0_sts[GPE_31_0], ps->gpe0_en[GPE_31_0], 0);
|
|
pch_log_gpio_gpe(ps->gpe0_sts[GPE_63_32], ps->gpe0_en[GPE_63_32], 32);
|
|
pch_log_gpio_gpe(ps->gpe0_sts[GPE_95_64], ps->gpe0_en[GPE_95_64], 64);
|
|
/* Treat the STD as an extension of GPIO to obtain visibility. */
|
|
pch_log_gpio_gpe(ps->gpe0_sts[GPE_STD], ps->gpe0_en[GPE_STD], 96);
|
|
}
|
|
|
|
static void pch_log_power_and_resets(struct chipset_power_state *ps)
|
|
{
|
|
/* Thermal Trip */
|
|
if (ps->gblrst_cause[0] & GBLRST_CAUSE0_THERMTRIP)
|
|
elog_add_event(ELOG_TYPE_THERM_TRIP);
|
|
|
|
/* PWR_FLR Power Failure */
|
|
if (ps->gen_pmcon_a & PWR_FLR)
|
|
elog_add_event(ELOG_TYPE_POWER_FAIL);
|
|
|
|
/* SUS Well Power Failure */
|
|
if (ps->gen_pmcon_a & SUS_PWR_FLR)
|
|
elog_add_event(ELOG_TYPE_SUS_POWER_FAIL);
|
|
|
|
/* TCO Timeout */
|
|
if (ps->prev_sleep_state != ACPI_S3 &&
|
|
ps->tco2_sts & TCO_STS_SECOND_TO)
|
|
elog_add_event(ELOG_TYPE_TCO_RESET);
|
|
|
|
/* Power Button Override */
|
|
if (ps->pm1_sts & PRBTNOR_STS)
|
|
elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE);
|
|
|
|
/* RTC reset */
|
|
if (ps->gen_pmcon_b & RTC_BATTERY_DEAD)
|
|
elog_add_event(ELOG_TYPE_RTC_RESET);
|
|
|
|
/* Host Reset Status */
|
|
if (ps->gen_pmcon_a & HOST_RST_STS)
|
|
elog_add_event(ELOG_TYPE_SYSTEM_RESET);
|
|
|
|
/* ACPI Wake Event */
|
|
if (ps->prev_sleep_state != ACPI_S0)
|
|
elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, ps->prev_sleep_state);
|
|
}
|
|
|
|
static void pch_log_state(void *unused)
|
|
{
|
|
struct chipset_power_state *ps = pmc_get_power_state();
|
|
|
|
if (!ps) {
|
|
printk(BIOS_ERR, "chipset_power_state not found!\n");
|
|
return;
|
|
}
|
|
|
|
/* Power and Reset */
|
|
pch_log_power_and_resets(ps);
|
|
|
|
/* Wake Sources */
|
|
if (ps->prev_sleep_state > ACPI_S0)
|
|
pch_log_wake_source(ps);
|
|
}
|
|
|
|
BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, pch_log_state, NULL);
|
|
|
|
void elog_gsmi_cb_platform_log_wake_source(void)
|
|
{
|
|
struct chipset_power_state ps;
|
|
pmc_fill_pm_reg_info(&ps);
|
|
pch_log_wake_source(&ps);
|
|
}
|