e30c396ffa
Unused includes found using following commande: diff <(git grep -l '#include <stddef.h>' -- src/) <(git grep -l 'size_t\|ssize_t\|wchar_t\|wint_t\|NULL\|DEVTREE_EARLY\|DEVTREE_CONST\ |MAYBE_STATIC_NONZERO\|MAYBE_STATIC_BSS\|zeroptr' -- src/)|grep '<' |grep -v vendor |grep -vF '.h' Change-Id: Ic54b1db995fe7c61b416fa5e1c4022238e4a6ad5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41150 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
90 lines
2.1 KiB
C
90 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <delay.h>
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#include <device/mmio.h>
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#include <console/console.h>
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#include <console/uart.h>
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#include <soc/addressmap.h>
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#include <soc/otp.h>
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/*
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* This is a driver for the eMemory EG004K32TQ028XW01 NeoFuse
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* One-Time-Programmable (OTP) memory used within the SiFive FU540.
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* It is documented in the FU540 manual here:
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* https://www.sifive.com/documentation/chips/freedom-u540-c000-manual/
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*/
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struct sifive_otp_registers {
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u32 pa; /* Address input */
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u32 paio; /* Program address input */
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u32 pas; /* Program redundancy cell selection input */
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u32 pce; /* OTP Macro enable input */
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u32 pclk; /* Clock input */
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u32 pdin; /* Write data input */
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u32 pdout; /* Read data output */
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u32 pdstb; /* Deep standby mode enable input (active low) */
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u32 pprog; /* Program mode enable input */
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u32 ptc; /* Test column enable input */
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u32 ptm; /* Test mode enable input */
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u32 ptm_rep;/* Repair function test mode enable input */
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u32 ptr; /* Test row enable input */
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u32 ptrim; /* Repair function enable input */
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u32 pwe; /* Write enable input (defines program cycle) */
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} __packed;
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/*
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* Read a 32 bit value addressed by its index from the OTP.
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* The FU540 stores 4096x32 bit (16KiB) values.
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* Index 0x00-0xff are reserved for SiFive internal use. (first 1KiB)
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*/
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u32 otp_read_word(u16 idx)
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{
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u32 w;
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if (idx >= 0x1000)
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die("otp: idx out of bounds");
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struct sifive_otp_registers *regs = (void *)(FU540_OTP);
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// wake up from stand-by
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write32(®s->pdstb, 0x01);
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// enable repair function
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write32(®s->ptrim, 0x01);
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// enable input
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write32(®s->pce, 0x01);
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// address to read
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write32(®s->pa, idx);
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// cycle clock to read
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write32(®s->pclk, 0x01);
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mdelay(1);
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write32(®s->pclk, 0x00);
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mdelay(1);
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w = read32(®s->pdout);
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// shut down
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write32(®s->pce, 0x00);
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write32(®s->ptrim, 0x00);
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write32(®s->pdstb, 0x00);
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return w;
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}
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u32 otp_read_serial(void)
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{
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u32 serial = 0;
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u32 serial_n = 0;
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for (int i = 0xfe; i > 0; i -= 2) {
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serial = otp_read_word(i);
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serial_n = otp_read_word(i+1);
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if (serial == ~serial_n)
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break;
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}
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return serial;
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}
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