6b5bc77c9b
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
120 lines
4.6 KiB
C
120 lines
4.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <intelblocks/gpio.h>
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#include <intelblocks/pcr.h>
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#include <soc/pcr.h>
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#include <soc/pm.h>
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static const struct reset_mapping rst_map[] = {
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{ .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
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{ .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
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{ .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
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/* (applicable only for GPD group) */
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{ .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 },
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};
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static const struct pad_group dnv_community_nc_groups[] = {
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INTEL_GPP(NORTH_ALL_GBE0_SDP0, NORTH_ALL_GBE0_SDP0, NORTH_ALL_PCIE_CLKREQ3_N),
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INTEL_GPP(NORTH_ALL_GBE0_SDP0, NORTH_ALL_PCIE_CLKREQ4_N, NORTH_ALL_MEMHOT_N),
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};
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static const struct pad_group dnv_community_sc_dfx_groups[] = {
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INTEL_GPP(SOUTH_DFX_DFX_PORT_CLK0, SOUTH_DFX_DFX_PORT_CLK0, SOUTH_DFX_DFX_PORT15),
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};
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static const struct pad_group dnv_community_sc0_groups[] = {
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INTEL_GPP(SOUTH_GROUP0_SMB3_CLTT_DATA, SOUTH_GROUP0_SMB3_CLTT_DATA, SOUTH_GROUP0_SATA0_LED_N),
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INTEL_GPP(SOUTH_GROUP0_SMB3_CLTT_DATA, SOUTH_GROUP0_SATA1_LED_N, SOUTH_GROUP0_DFX_SPARE4),
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};
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static const struct pad_group dnv_community_sc1_groups[] = {
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INTEL_GPP(SOUTH_GROUP1_SUSPWRDNACK, SOUTH_GROUP1_SUSPWRDNACK, SOUTH_GROUP1_EMMC_STROBE),
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INTEL_GPP(SOUTH_GROUP1_SUSPWRDNACK, SOUTH_GROUP1_EMMC_CLK, SOUTH_GROUP1_GPIO_3),
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};
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static const struct pad_community dnv_gpio_communities[] = {
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{
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.port = PID_GPIOCOM1,
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.first_pad = SOUTH_GROUP1_SUSPWRDNACK,
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.last_pad = SOUTH_GROUP1_GPIO_3,
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.num_gpi_regs = NUM_SC1_GPI_REGS,
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.gpi_status_offset = NUM_NC_GPI_REGS + NUM_SC_DFX_GPI_REGS +
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NUM_SC0_GPI_REGS,
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.pad_cfg_base = R_PCH_PCR_GPIO_SC1_PADCFG_OFFSET,
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.host_own_reg_0 = R_PCH_PCR_GPIO_SC1_PAD_OWN,
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.gpi_int_sts_reg_0 = R_PCH_PCR_GPIO_SC1_GPI_IS,
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.gpi_int_en_reg_0 = R_PCH_PCR_GPIO_SC1_GPI_IE,
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.gpi_smi_sts_reg_0 = R_PCH_PCR_GPIO_SC1_GPI_GPE_STS,
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.gpi_smi_en_reg_0 = R_PCH_PCR_GPIO_SC1_GPI_GPE_EN,
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.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
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.name = "GPIO_GPE_SC1",
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.acpi_path = "\\_SB.GPO3",
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.reset_map = rst_map,
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.num_reset_vals = ARRAY_SIZE(rst_map),
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.groups = dnv_community_sc1_groups,
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.num_groups = ARRAY_SIZE(dnv_community_sc1_groups),
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}, {
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.port = PID_GPIOCOM1,
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.first_pad = SOUTH_GROUP0_SMB3_CLTT_DATA,
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.last_pad = SOUTH_GROUP0_DFX_SPARE4,
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.num_gpi_regs = NUM_SC0_GPI_REGS,
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.gpi_status_offset = NUM_NC_GPI_REGS + NUM_SC_DFX_GPI_REGS,
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.pad_cfg_base = R_PCH_PCR_GPIO_SC0_PADCFG_OFFSET,
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.host_own_reg_0 = R_PCH_PCR_GPIO_SC0_PAD_OWN,
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.gpi_int_sts_reg_0 = R_PCH_PCR_GPIO_SC0_GPI_IS,
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.gpi_int_en_reg_0 = R_PCH_PCR_GPIO_SC0_GPI_IE,
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.gpi_smi_sts_reg_0 = R_PCH_PCR_GPIO_SC0_GPI_GPE_STS,
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.gpi_smi_en_reg_0 = R_PCH_PCR_GPIO_SC0_GPI_GPE_EN,
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.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
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.name = "GPIO_GPE_SC0",
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.acpi_path = "\\_SB.GPO2",
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.reset_map = rst_map,
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.num_reset_vals = ARRAY_SIZE(rst_map),
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.groups = dnv_community_sc0_groups,
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.num_groups = ARRAY_SIZE(dnv_community_sc0_groups),
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}, {
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.port = PID_GPIOCOM1,
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.first_pad = SOUTH_DFX_DFX_PORT_CLK0,
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.last_pad = SOUTH_DFX_DFX_PORT15,
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.num_gpi_regs = NUM_SC_DFX_GPI_REGS,
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.gpi_status_offset = NUM_NC_GPI_REGS,
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.pad_cfg_base = R_PCH_PCR_GPIO_SC_DFX_PADCFG_OFFSET,
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.host_own_reg_0 = R_PCH_PCR_GPIO_SC_DFX_HOSTSW_OWN,
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.gpi_int_sts_reg_0 = R_PCH_PCR_GPIO_SC_DFX_GPI_IS,
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.gpi_int_en_reg_0 = R_PCH_PCR_GPIO_SC_DFX_GPI_IE,
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.gpi_smi_sts_reg_0 = R_PCH_PCR_GPIO_SC_DFX_GPI_GPE_STS,
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.gpi_smi_en_reg_0 = R_PCH_PCR_GPIO_SC_DFX_GPI_GPE_EN,
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.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
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.name = "GPIO_GPE_SC_DFX",
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.acpi_path = "\\_SB.GPO1",
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.reset_map = rst_map,
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.num_reset_vals = ARRAY_SIZE(rst_map),
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.groups = dnv_community_sc_dfx_groups,
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.num_groups = ARRAY_SIZE(dnv_community_sc_dfx_groups),
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}, {
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.port = PID_GPIOCOM0,
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.first_pad = NORTH_ALL_GBE0_SDP0,
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.last_pad = NORTH_ALL_MEMHOT_N,
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.num_gpi_regs = NUM_NC_GPI_REGS,
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.gpi_status_offset = 0,
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.pad_cfg_base = R_PCH_PCR_GPIO_NC_PADCFG_OFFSET,
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.host_own_reg_0 = R_PCH_PCR_GPIO_NC_PAD_OWN,
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.gpi_int_sts_reg_0 = R_PCH_PCR_GPIO_NC_GPI_IS,
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.gpi_int_en_reg_0 = R_PCH_PCR_GPIO_NC_GPI_IE,
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.gpi_smi_sts_reg_0 = R_PCH_PCR_GPIO_NC_GPI_GPE_STS,
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.gpi_smi_en_reg_0 = R_PCH_PCR_GPIO_NC_GPI_GPE_EN,
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.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
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.name = "GPIO_GPE_NC",
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.acpi_path = "\\_SB.GPO0",
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.reset_map = rst_map,
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.num_reset_vals = ARRAY_SIZE(rst_map),
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.groups = dnv_community_nc_groups,
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.num_groups = ARRAY_SIZE(dnv_community_nc_groups),
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}
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};
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const struct pad_community *soc_gpio_get_community(size_t *num_communities)
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{
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*num_communities = ARRAY_SIZE(dnv_gpio_communities);
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return dnv_gpio_communities;
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}
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