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coreboot-kgpe-d16/src/southbridge/intel/bd82x6x
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Vladimir Serbinenko 6d6298dddc ibexpeak / bd82x6x: Make SATA mode user-visible option. 
Ability to choose compatibility mode is interesting for testing payloads and
OS for compatibility with older systems.

As per comments
"ide_legacy_combined # TODO: Does nothing since
		      generations, remove from sb code?"
The "combined" mode was removed. It wasn't used by any mobo and the code for
it is almost identical to IDE one other than few bits relating to interrupt
handling and ISA mode.

Change-Id: I407a8fac753b513812a86bef5abcf39c6d81472e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4658
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12 18:03:23 +01:00
..
acpi Add Intel Panther Point USB3 initialization 2013-03-09 00:09:37 +01:00
azalia.c intel/sandybridge intel/bd82x6x: remove explicit pcie config accesses 2013-08-09 23:20:52 +02:00
bootblock.c x86: Unify arch/io.h and arch/romcc_io.h 2013-03-22 00:00:09 +01:00
chip.h ibexpeak / bd82x6x: Make SATA mode user-visible option. 2014-01-12 18:03:23 +01:00
early_me.c x86: Unify arch/io.h and arch/romcc_io.h 2013-03-22 00:00:09 +01:00
early_pch.c timestamps intel: Move timestamp scratchpad to chipset 2013-09-21 06:20:02 +02:00
early_smbus.c x86: Unify arch/io.h and arch/romcc_io.h 2013-03-22 00:00:09 +01:00
early_spi.c x86: Unify arch/io.h and arch/romcc_io.h 2013-03-22 00:00:09 +01:00
early_usb.c bd82x6x: Fix early USB BAR programming (finally?) 2013-06-25 18:50:55 +02:00
elog.c ELOG: Log boot-time events found in southbridge 2012-07-25 22:25:22 +02:00
finalize.c intel/sandybridge intel/bd82x6x: remove explicit pcie config accesses 2013-08-09 23:20:52 +02:00
gpio.c x86: Unify arch/io.h and arch/romcc_io.h 2013-03-22 00:00:09 +01:00
gpio.h Provide functions to access arbitrary GPIO pins and vectors 2012-05-30 00:53:19 +02:00
Kconfig bd82x6x/ibexpeak: Make DRAM reset gate GPIO configurable 2014-01-09 17:16:12 +01:00
lpc.c Intel BD82x6x: LPC: Unify I/O APIC setup 2013-06-03 08:21:54 +02:00
Makefile.inc timestamps intel: Move timestamp scratchpad to chipset 2013-09-21 06:20:02 +02:00
me.c intel/sandybridge intel/bd82x6x: remove explicit pcie config accesses 2013-08-09 23:20:52 +02:00
me.h Cougar/Panther Point: Compile in ME7 and ME8 code at the same time 2012-07-24 23:17:17 +02:00
me_8.x.c intel/sandybridge intel/bd82x6x: remove explicit pcie config accesses 2013-08-09 23:20:52 +02:00
me_status.c Add support for Intel Panther Point PCH 2012-04-04 19:10:51 +02:00
nvs.h Add Intel Panther Point USB3 initialization 2013-03-09 00:09:37 +01:00
pch.c x86: Unify arch/io.h and arch/romcc_io.h 2013-03-22 00:00:09 +01:00
pch.h Intel BD82x6x: LPC: Unify I/O APIC setup 2013-06-03 08:21:54 +02:00
pci.c GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« 2013-03-01 10:16:08 +01:00
pcie.c intel/sandybridge intel/bd82x6x: remove explicit pcie config accesses 2013-08-09 23:20:52 +02:00
reset.c GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« 2013-03-01 10:16:08 +01:00
sata.c ibexpeak / bd82x6x: Make SATA mode user-visible option. 2014-01-12 18:03:23 +01:00
smbus.c GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« 2013-03-01 10:16:08 +01:00
smbus.h GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« 2013-03-01 10:16:08 +01:00
smi.c intel/*/smi.c: Output correct GPIO in ALT_GP_SMI_STS register dump 2013-06-12 01:54:19 +02:00
smihandler.c bd82x6x/ibexpeak: Make DRAM reset gate GPIO configurable 2014-01-09 17:16:12 +01:00
spi.c intel/sandybridge intel/bd82x6x: remove explicit pcie config accesses 2013-08-09 23:20:52 +02:00
usb_ehci.c usbdebug: Drop duplicates of EHCI BAR relocation code 2013-07-01 17:10:55 +02:00
usb_xhci.c Pantherpoint: Add XHCI device init 2013-03-17 22:51:05 +01:00
watchdog.c GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« 2013-03-01 10:16:08 +01:00