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Marc Jones 6dcb6c2fa4 soc/amd/stoneyridge: Add IGFX device ACPI ASL entry
Add internal graphics device 00.01.00 to the ACPI tables so that the
ACPI PCI option ROM save functions have a proper scope to save the
ROM to.

BUG=b:111697181
TEST=Check coreboot log doesn't have "PCI: 00:01.0: Missing ACPI scope"
and check _ROM method is added in the SSDT1.

Change-Id: I2c9ef8d9dff76805b1fcde2ccceef958a5b53b4f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/27653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-07-27 20:12:58 +00:00
3rdparty 3rdparty/blobs: Update submodule pointer to pull in latest changes 2018-07-27 03:00:43 +00:00
Documentation util: Add util_readme script 2018-07-26 13:26:29 +00:00
configs configs: add PC Engines apu2 sample configuration 2018-05-19 16:55:56 +00:00
payloads libpayload/arm64: Drop unused static array 2018-07-20 11:06:36 +00:00
src soc/amd/stoneyridge: Add IGFX device ACPI ASL entry 2018-07-27 20:12:58 +00:00
util cbfstool: fix implicit declaration of strcasecmp 2018-07-27 10:48:17 +00:00
.checkpatch.conf .checkpatch.conf: Ignore CORRUPTED_PATCH lint 2017-10-29 10:11:58 +00:00
.clang-format clang-format: Update .clang-format to be compliant with linux kernel coding style 2018-04-23 09:26:08 +00:00
.gitignore Documentation: Add support for building with Sphinx 2018-04-26 12:25:03 +00:00
.gitmodules
.gitreview
COPYING
MAINTAINERS MAINTAINERS: change second PC Engines maintainer 2018-03-21 18:25:49 +00:00
Makefile Makefile: Add filelist to help 2018-01-29 15:35:11 +00:00
Makefile.inc Build system: Add fixes for scanbuild 2018-07-24 09:08:55 +00:00
README
gnat.adc
toolchain.inc Introduce bootblock self-decompression 2018-05-22 02:44:14 +00:00

README

-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------

coreboot is a Free Software project aimed at replacing the proprietary BIOS
(firmware) found in most computers.  coreboot performs a little bit of
hardware initialization and then executes additional boot logic, called a
payload.

With the separation of hardware initialization and later boot logic,
coreboot can scale from specialized applications that run directly
firmware, run operating systems in flash, load custom
bootloaders, or implement firmware standards, like PC BIOS services or
UEFI. This allows for systems to only include the features necessary
in the target application, reducing the amount of code and flash space
required.

coreboot was formerly known as LinuxBIOS.


Payloads
--------

After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.


Supported Hardware
------------------

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

 * https://www.coreboot.org/Supported_Motherboards
 * https://www.coreboot.org/Supported_Chipsets_and_Devices


Build Requirements
------------------

 * make
 * gcc / g++
   Because Linux distribution compilers tend to use lots of patches. coreboot
   does lots of "unusual" things in its build system, some of which break due
   to those patches, sometimes by gcc aborting, sometimes - and that's worse -
   by generating broken object code.
   Two options: use our toolchain (eg. make crosstools-i386) or enable the
   ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this
   case).
 * iasl (for targets with ACPI support)
 * pkg-config
 * libssl-dev (openssl)

Optional:

 * doxygen (for generating/viewing documentation)
 * gdb (for better debugging facilities on some targets)
 * ncurses (for 'make menuconfig' and 'make nconfig')
 * flex and bison (for regenerating parsers)


Building coreboot
-----------------

Please consult https://www.coreboot.org/Build_HOWTO for details.


Testing coreboot Without Modifying Your Hardware
------------------------------------------------

If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.


Website and Mailing List
------------------------

Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:

  https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

  https://www.coreboot.org/Mailinglist


Copyright and License
---------------------

The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.