71d227b108
Refactor GPIO code which will be reused among similar SOCs. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Elm Change-Id: Icdd1f2a1dd1bd64a7218bf9c63bd4a0af1acbcc0 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
53 lines
1.5 KiB
C
53 lines
1.5 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2015 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <boardid.h>
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#include <bootmode.h>
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#include <boot/coreboot_tables.h>
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#include <gpio.h>
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#include <string.h>
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#include "gpio.h"
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void setup_chromeos_gpios(void)
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{
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gpio_input(WRITE_PROTECT);
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gpio_input_pullup(EC_IN_RW);
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gpio_input_pullup(EC_IRQ);
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gpio_input(LID);
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gpio_input_pullup(POWER_BUTTON);
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if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 5)
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gpio_output(EC_SUSPEND_L, 1);
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}
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void fill_lb_gpios(struct lb_gpios *gpios)
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{
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struct lb_gpio chromeos_gpios[] = {
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{WRITE_PROTECT.id, ACTIVE_LOW,
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gpio_get(WRITE_PROTECT), "write protect"},
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{-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
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{LID.id, ACTIVE_HIGH, -1, "lid"},
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{POWER_BUTTON.id, ACTIVE_HIGH, -1, "power"},
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{EC_IN_RW.id, ACTIVE_HIGH, -1, "EC in RW"},
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{EC_IRQ.id, ACTIVE_LOW, -1, "EC interrupt"},
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{CR50_IRQ.id, ACTIVE_HIGH, -1, "TPM interrupt"},
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};
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lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
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}
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int get_write_protect_state(void)
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{
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return !gpio_get(WRITE_PROTECT);
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}
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