aa33609d28
dwc2 host core do not have a periodic schedule list, so try to send an interrupt packet in poll_intr_queue() function and use frame number read from usb core register to calculate time and schedule transfers. BUG=None TEST=Tested on RK3288 with two USB keyboards(connect to SoC without USB hub), both work correctly. BRANCH=None Change-Id: I16f7977c45a84b37c32b7c495ca78ad76be9f0ce Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3d0206b86634bcfdbe03da3e2c8adf186470e157 Original-Change-Id: Ie54699162ef799f4d3d2a0abf850dbeb62417777 Original-Signed-off-by: Yunzhi Li <lyz@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/280750 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Lin Huang <hl@rock-chips.com> Original-Tested-by: Lin Huang <hl@rock-chips.com> Reviewed-on: http://review.coreboot.org/10774 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
50 lines
1.3 KiB
C
50 lines
1.3 KiB
C
/*
|
|
* This file is part of the coreboot project.
|
|
*
|
|
* Copyright (C) 2014 Rockchip Electronics
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License as published by
|
|
* the Free Software Foundation; version 2 of the License.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program; if not, write to the Free Software
|
|
* Foundation, Inc.
|
|
*/
|
|
|
|
#ifndef __DWC2_REGS_H__
|
|
#define __DWC2_REGS_H__
|
|
#include <usb/dwc2_registers.h>
|
|
|
|
typedef struct dwc_ctrl {
|
|
#define DMA_SIZE (64 * 1024)
|
|
void *dma_buffer;
|
|
u32 *hprt0;
|
|
u32 frame;
|
|
} dwc_ctrl_t;
|
|
|
|
typedef struct {
|
|
u8 *data;
|
|
endpoint_t *endp;
|
|
int reqsize;
|
|
u32 reqtiming;
|
|
u32 timestamp;
|
|
} intr_queue_t;
|
|
|
|
#define DWC2_INST(controller) ((dwc_ctrl_t *)((controller)->instance))
|
|
#define DWC2_REG(controller) ((dwc2_reg_t *)((controller)->reg_base))
|
|
|
|
typedef enum {
|
|
HCSTAT_DONE = 0,
|
|
HCSTAT_XFERERR,
|
|
HCSTAT_BABBLE,
|
|
HCSTAT_STALL,
|
|
HCSTAT_UNKNOW,
|
|
HCSTAT_TIMEOUT,
|
|
} hcstat_t;
|
|
#endif
|