Huayang Duan 6e57b1cf6d soc/mediatek/mt8183: Transfer ddr geometry type to dram blob ... BUG=none BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: I3a677195f5036321939c60c8f9f1bace7c4a2e3f Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>		2020-08-12 02:50:59 +00:00
..
acpi	src/acpi: Add missing <{stdbool,stdint}.h>	2020-07-29 09:37:10 +00:00
arch	arch/x86/pirq_routing.c: Drop unneeded continue	2020-08-06 11:22:11 +00:00
commonlib	src: Remove unused 'include <stdint.h>	2020-07-14 16:11:10 +00:00
console
cpu	cpu/intel: Remove Core 2 Duo E8200 CPUID from model_6fx	2020-08-11 21:43:47 +00:00
device	src: Use space after 'if', 'for'	2020-08-05 11:37:00 +00:00
drivers	drivers/intel/fsp2_0: Do AP re-init after FSP-S if USE_INTEL_FSP_MP_INIT enable	2020-08-06 04:24:24 +00:00
ec	ec/lenovo/h8: Align macro values in one column	2020-07-26 21:40:00 +00:00
include	soc/intel/common: Include Alder Lake SATA controller device IDs	2020-08-10 06:30:39 +00:00
lib	gpio: Pull down HiZ pins after reading tristate GPIO strapping	2020-08-06 23:54:41 +00:00
mainboard	vendorcode/intel/fsp/fsp2_0/CPX-SP: remove non-existing PSTACKs	2020-08-11 20:15:30 +00:00
northbridge	nb/intel/sandybridge/raminit: Add comments	2020-08-11 12:03:09 +00:00
security	security/intel/txt: Fix variable MTRR handling	2020-08-07 11:56:29 +00:00
soc	soc/mediatek/mt8183: Transfer ddr geometry type to dram blob	2020-08-12 02:50:59 +00:00
southbridge	sb/intel/lynxpoint: Use PCI bitwise ops	2020-08-07 11:02:43 +00:00
superio	superio/ite: allow 24 MHz clock for external sensor interface	2020-08-10 12:44:17 +00:00
vendorcode	vendorcode/intel/fsp/fsp2_0/CPX-SP: remove non-existing PSTACKs	2020-08-11 20:15:30 +00:00
Kconfig