a46a712610
In the file `COPYING` in the coreboot repository and upstream [1]
just one space is used.
The following command was used to convert all files.
$ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/'
[1] http://www.gnu.org/licenses/gpl-2.0.txt
Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2490
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
566 lines
16 KiB
C
566 lines
16 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* 2012 secunet Security Networks AG
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <pc80/mc146818rtc.h>
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#include <pc80/isa-dma.h>
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#include <pc80/i8259.h>
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#include <arch/io.h>
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#include <arch/ioapic.h>
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#include <arch/acpi.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/smm.h>
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#include "i82801ix.h"
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#define NMI_OFF 0
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#define ENABLE_ACPI_MODE_IN_COREBOOT 0
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#define TEST_SMM_FLASH_LOCKDOWN 0
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typedef struct southbridge_intel_i82801ix_config config_t;
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static void i82801ix_enable_apic(struct device *dev)
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{
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u8 dummy;
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u32 reg32;
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volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
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volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
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/* Enable IOAPIC. Keep APIC Range Select at zero. */
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RCBA8(0x31ff) = 0x03;
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/* We have to read 0x31ff back if bit0 changed. */
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dummy = RCBA8(0x31ff);
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/* Lock maximum redirection entries (MRE), R/WO register. */
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*ioapic_index = 0x01;
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reg32 = *ioapic_data;
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*ioapic_index = 0x01;
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*ioapic_data = reg32;
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setup_ioapic(IO_APIC_ADDR, 2); /* ICH7 code uses id 2. */
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}
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static void i82801ix_enable_serial_irqs(struct device *dev)
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{
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/* Set packet length and toggle silent mode bit for one frame. */
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pci_write_config8(dev, D31F0_SERIRQ_CNTL,
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(1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
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}
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/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
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* 0x00 - 0000 = Reserved
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* 0x01 - 0001 = Reserved
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* 0x02 - 0010 = Reserved
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* 0x03 - 0011 = IRQ3
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* 0x04 - 0100 = IRQ4
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* 0x05 - 0101 = IRQ5
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* 0x06 - 0110 = IRQ6
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* 0x07 - 0111 = IRQ7
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* 0x08 - 1000 = Reserved
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* 0x09 - 1001 = IRQ9
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* 0x0A - 1010 = IRQ10
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* 0x0B - 1011 = IRQ11
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* 0x0C - 1100 = IRQ12
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* 0x0D - 1101 = Reserved
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* 0x0E - 1110 = IRQ14
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* 0x0F - 1111 = IRQ15
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* PIRQ[n]_ROUT[7] - PIRQ Routing Control
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* 0x80 - The PIRQ is not routed.
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*/
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static void i82801ix_pirq_init(device_t dev)
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{
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device_t irq_dev;
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/* Get the chip configuration */
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config_t *config = dev->chip_info;
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pci_write_config8(dev, D31F0_PIRQA_ROUT, config->pirqa_routing);
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pci_write_config8(dev, D31F0_PIRQB_ROUT, config->pirqb_routing);
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pci_write_config8(dev, D31F0_PIRQC_ROUT, config->pirqc_routing);
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pci_write_config8(dev, D31F0_PIRQD_ROUT, config->pirqd_routing);
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pci_write_config8(dev, D31F0_PIRQE_ROUT, config->pirqe_routing);
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pci_write_config8(dev, D31F0_PIRQF_ROUT, config->pirqf_routing);
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pci_write_config8(dev, D31F0_PIRQG_ROUT, config->pirqg_routing);
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pci_write_config8(dev, D31F0_PIRQH_ROUT, config->pirqh_routing);
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/* Eric Biederman once said we should let the OS do this.
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* I am not so sure anymore he was right.
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*/
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for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
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u8 int_pin=0, int_line=0;
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if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
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continue;
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int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
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switch (int_pin) {
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case 1: /* INTA# */ int_line = config->pirqa_routing; break;
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case 2: /* INTB# */ int_line = config->pirqb_routing; break;
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case 3: /* INTC# */ int_line = config->pirqc_routing; break;
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case 4: /* INTD# */ int_line = config->pirqd_routing; break;
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}
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if (!int_line)
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continue;
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pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
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}
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}
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static void i82801ix_gpi_routing(device_t dev)
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{
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/* Get the chip configuration */
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config_t *config = dev->chip_info;
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u32 reg32 = 0;
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/* An array would be much nicer here, or some
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* other method of doing this.
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*/
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reg32 |= (config->gpi0_routing & 0x03) << 0;
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reg32 |= (config->gpi1_routing & 0x03) << 2;
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reg32 |= (config->gpi2_routing & 0x03) << 4;
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reg32 |= (config->gpi3_routing & 0x03) << 6;
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reg32 |= (config->gpi4_routing & 0x03) << 8;
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reg32 |= (config->gpi5_routing & 0x03) << 10;
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reg32 |= (config->gpi6_routing & 0x03) << 12;
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reg32 |= (config->gpi7_routing & 0x03) << 14;
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reg32 |= (config->gpi8_routing & 0x03) << 16;
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reg32 |= (config->gpi9_routing & 0x03) << 18;
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reg32 |= (config->gpi10_routing & 0x03) << 20;
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reg32 |= (config->gpi11_routing & 0x03) << 22;
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reg32 |= (config->gpi12_routing & 0x03) << 24;
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reg32 |= (config->gpi13_routing & 0x03) << 26;
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reg32 |= (config->gpi14_routing & 0x03) << 28;
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reg32 |= (config->gpi15_routing & 0x03) << 30;
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pci_write_config32(dev, D31F0_GPIO_ROUT, reg32);
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}
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static void i82801ix_power_options(device_t dev)
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{
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u8 reg8;
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u16 reg16, pmbase;
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u32 reg32;
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const char *state;
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/* Get the chip configuration */
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config_t *config = dev->chip_info;
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int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
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int nmi_option;
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/* BIOS must program... */
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reg32 = pci_read_config32(dev, 0xac);
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pci_write_config32(dev, 0xac, reg32 | (1 << 30) | (3 << 8));
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/* Which state do we want to goto after g3 (power restored)?
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* 0 == S0 Full On
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* 1 == S5 Soft Off
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*
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* If the option is not existent (Laptops), use MAINBOARD_POWER_ON.
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*/
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if (get_option(&pwr_on, "power_on_after_fail") < 0)
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pwr_on = MAINBOARD_POWER_ON;
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reg8 = pci_read_config8(dev, D31F0_GEN_PMCON_3);
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reg8 &= 0xfe;
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switch (pwr_on) {
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case MAINBOARD_POWER_OFF:
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reg8 |= 1;
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state = "off";
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break;
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case MAINBOARD_POWER_ON:
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reg8 &= ~1;
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state = "on";
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break;
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case MAINBOARD_POWER_KEEP:
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reg8 &= ~1;
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state = "state keep";
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break;
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default:
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state = "undefined";
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}
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reg8 |= (3 << 4); /* avoid #S4 assertions */
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reg8 &= ~(1 << 3); /* minimum asssertion is 1 to 2 RTCCLK */
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pci_write_config8(dev, D31F0_GEN_PMCON_3, reg8);
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printk(BIOS_INFO, "Set power %s after power failure.\n", state);
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/* Set up NMI on errors. */
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reg8 = inb(0x61);
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reg8 &= 0x0f; /* Higher Nibble must be 0 */
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reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */
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// reg8 &= ~(1 << 2); /* PCI SERR# Enable */
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reg8 |= (1 << 2); /* PCI SERR# Disable for now */
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outb(reg8, 0x61);
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reg8 = inb(0x74); /* Read from 0x74 as 0x70 is write only. */
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nmi_option = NMI_OFF;
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get_option(&nmi_option, "nmi");
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if (nmi_option) {
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printk(BIOS_INFO, "NMI sources enabled.\n");
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reg8 &= ~(1 << 7); /* Set NMI. */
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} else {
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printk(BIOS_INFO, "NMI sources disabled.\n");
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reg8 |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */
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}
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outb(reg8, 0x70);
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/* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */
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reg16 = pci_read_config16(dev, D31F0_GEN_PMCON_1);
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reg16 &= ~(3 << 0); // SMI# rate 1 minute
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reg16 |= (1 << 2); // CLKRUN_EN - Mobile/Ultra only
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reg16 |= (1 << 3); // Speedstep Enable - Mobile/Ultra only
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reg16 |= (1 << 5); // CPUSLP_EN Desktop only
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if (config->c4onc3_enable)
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reg16 |= (1 << 7);
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// another laptop wants this?
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// reg16 &= ~(1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only
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reg16 |= (1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only
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#if DEBUG_PERIODIC_SMIS
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/* Set DEBUG_PERIODIC_SMIS in i82801ix.h to debug using
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* periodic SMIs.
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*/
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reg16 |= (3 << 0); // Periodic SMI every 8s
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#endif
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if (config->c5_enable)
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reg16 |= (1 << 11); /* Enable C5, C6 and PMSYNC# */
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pci_write_config16(dev, D31F0_GEN_PMCON_1, reg16);
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/* Set exit timings for C5/C6. */
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if (config->c5_enable) {
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reg8 = pci_read_config8(dev, D31F0_C5_EXIT_TIMING);
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reg8 &= ~((7 << 3) | (7 << 0));
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if (config->c6_enable)
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reg8 |= (5 << 3) | (3 << 0); /* 38-44us PMSYNC# to STPCLK#,
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95-102us DPRSTP# to STP_CPU# */
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else
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reg8 |= (0 << 3) | (1 << 0); /* 16-17us PMSYNC# to STPCLK#,
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34-40us DPRSTP# to STP_CPU# */
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pci_write_config8(dev, D31F0_C5_EXIT_TIMING, reg8);
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}
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// Set the board's GPI routing.
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i82801ix_gpi_routing(dev);
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pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
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outl(config->gpe0_en, pmbase + 0x28);
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outw(config->alt_gp_smi_en, pmbase + 0x38);
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/* Set up power management block and determine sleep mode */
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reg16 = inw(pmbase + 0x00); /* PM1_STS */
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outw(reg16, pmbase + 0x00); /* Clear status bits. At least bit11 (power
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button override) must be cleared or SCI
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will be constantly fired and OSPM must
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not know about it (ACPI spec says to
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ignore the bit). */
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reg32 = inl(pmbase + 0x04); // PM1_CNT
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reg32 &= ~(7 << 10); // SLP_TYP
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outl(reg32, pmbase + 0x04);
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/* Set duty cycle for hardware throttling (defaults to 0x0: 50%). */
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reg32 = inl(pmbase + 0x10);
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reg32 &= ~(7 << 5);
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reg32 |= (config->throttle_duty & 7) << 5;
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outl(reg32, pmbase + 0x10);
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}
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static void i82801ix_configure_cstates(device_t dev)
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{
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u8 reg8;
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reg8 = pci_read_config8(dev, D31F0_CxSTATE_CNF);
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reg8 |= (1 << 4) | (1 << 3) | (1 << 2); // Enable Popup & Popdown
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pci_write_config8(dev, D31F0_CxSTATE_CNF, reg8);
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// Set Deeper Sleep configuration to recommended values
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reg8 = pci_read_config8(dev, D31F0_C4TIMING_CNT);
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reg8 &= 0xf0;
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reg8 |= (2 << 2); // Deeper Sleep to Stop CPU: 34-40us
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reg8 |= (2 << 0); // Deeper Sleep to Sleep: 15us
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pci_write_config8(dev, D31F0_C4TIMING_CNT, reg8);
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/* We could enable slow-C4 exit here, if someone needs it? */
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}
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static void i82801ix_rtc_init(struct device *dev)
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{
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u8 reg8;
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int rtc_failed;
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reg8 = pci_read_config8(dev, D31F0_GEN_PMCON_3);
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rtc_failed = reg8 & RTC_BATTERY_DEAD;
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if (rtc_failed) {
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reg8 &= ~RTC_BATTERY_DEAD;
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pci_write_config8(dev, D31F0_GEN_PMCON_3, reg8);
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}
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printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
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rtc_init(rtc_failed);
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}
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static void enable_hpet(void)
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{
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u32 reg32;
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/* Move HPET to default address 0xfed00000 and enable it */
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reg32 = RCBA32(RCBA_HPTC);
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reg32 |= (1 << 7); // HPET Address Enable
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reg32 &= ~(3 << 0);
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RCBA32(RCBA_HPTC) = reg32;
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}
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static void enable_clock_gating(void)
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{
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u32 reg32;
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/* Enable DMI dynamic clock gating. */
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RCBA32(RCBA_DMIC) |= 3;
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/* Enable Clock Gating for most devices. */
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reg32 = RCBA32(RCBA_CG);
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reg32 |= (1 << 31); /* LPC dynamic clock gating */
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/* USB UHCI dynamic clock gating: */
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reg32 |= (1 << 29) | (1 << 28);
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/* SATA dynamic clock gating [0-3]: */
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reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24);
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reg32 |= (1 << 23); /* LAN static clock gating (if LAN disabled) */
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reg32 |= (1 << 22); /* HD audio dynamic clock gating */
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reg32 &= ~(1 << 21); /* No HD audio static clock gating */
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reg32 &= ~(1 << 20); /* No USB EHCI static clock gating */
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reg32 |= (1 << 19); /* USB EHCI dynamic clock gating */
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/* More SATA dynamic clock gating [4-5]: */
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reg32 |= (1 << 18) | (1 << 17);
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reg32 |= (1 << 16); /* PCI dynamic clock gating */
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/* PCIe, DMI dynamic clock gating: */
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reg32 |= (1 << 4) | (1 << 3) | (1 << 2) | (1 << 1);
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reg32 |= (1 << 0); /* PCIe root port static clock gating */
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RCBA32(RCBA_CG) = reg32;
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/* Enable SPI dynamic clock gating. */
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RCBA32(0x38c0) |= 7;
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}
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#if CONFIG_HAVE_SMI_HANDLER
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static void i82801ix_lock_smm(struct device *dev)
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{
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#if TEST_SMM_FLASH_LOCKDOWN
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u8 reg8;
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#endif
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if (acpi_slp_type != 3) {
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#if ENABLE_ACPI_MODE_IN_COREBOOT
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printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
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outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode
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printk(BIOS_DEBUG, "done.\n");
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#else
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printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
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outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode
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printk(BIOS_DEBUG, "done.\n");
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#endif
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} else {
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printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n");
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outb(APM_CNT_ACPI_ENABLE, APM_CNT);
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}
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/* Don't allow evil boot loaders, kernels, or
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* userspace applications to deceive us:
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*/
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smm_lock();
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#if TEST_SMM_FLASH_LOCKDOWN
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/* Now try this: */
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printk(BIOS_DEBUG, "Locking BIOS to RO... ");
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reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
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printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
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(reg8&1)?"rw":"ro");
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reg8 &= ~(1 << 0); /* clear BIOSWE */
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pci_write_config8(dev, 0xdc, reg8);
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reg8 |= (1 << 1); /* set BLE */
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pci_write_config8(dev, 0xdc, reg8);
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printk(BIOS_DEBUG, "ok.\n");
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reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
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printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
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(reg8&1)?"rw":"ro");
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printk(BIOS_DEBUG, "Writing:\n");
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*(volatile u8 *)0xfff00000 = 0x00;
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printk(BIOS_DEBUG, "Testing:\n");
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reg8 |= (1 << 0); /* set BIOSWE */
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pci_write_config8(dev, 0xdc, reg8);
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reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
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printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
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|
(reg8&1)?"rw":"ro");
|
|
printk(BIOS_DEBUG, "Done.\n");
|
|
#endif
|
|
}
|
|
#endif
|
|
|
|
static void lpc_init(struct device *dev)
|
|
{
|
|
printk(BIOS_DEBUG, "i82801ix: lpc_init\n");
|
|
|
|
/* Set the value for PCI command register. */
|
|
pci_write_config16(dev, PCI_COMMAND, 0x000f);
|
|
|
|
/* IO APIC initialization. */
|
|
i82801ix_enable_apic(dev);
|
|
|
|
i82801ix_enable_serial_irqs(dev);
|
|
|
|
/* Setup the PIRQ. */
|
|
i82801ix_pirq_init(dev);
|
|
|
|
/* Setup power options. */
|
|
i82801ix_power_options(dev);
|
|
|
|
/* Configure Cx state registers */
|
|
if (LPC_IS_MOBILE(dev))
|
|
i82801ix_configure_cstates(dev);
|
|
|
|
/* Initialize the real time clock. */
|
|
i82801ix_rtc_init(dev);
|
|
|
|
/* Initialize ISA DMA. */
|
|
isa_dma_init();
|
|
|
|
/* Initialize the High Precision Event Timers, if present. */
|
|
enable_hpet();
|
|
|
|
/* Initialize Clock Gating */
|
|
enable_clock_gating();
|
|
|
|
setup_i8259();
|
|
|
|
/* The OS should do this? */
|
|
/* Interrupt 9 should be level triggered (SCI) */
|
|
i8259_configure_irq_trigger(9, 1);
|
|
|
|
#if CONFIG_HAVE_SMI_HANDLER
|
|
i82801ix_lock_smm(dev);
|
|
#endif
|
|
}
|
|
|
|
static void i82801ix_lpc_read_resources(device_t dev)
|
|
{
|
|
/*
|
|
* I/O Resources
|
|
*
|
|
* 0x0000 - 0x000f....ISA DMA
|
|
* 0x0010 - 0x001f....ISA DMA aliases
|
|
* 0x0020 ~ 0x003d....PIC
|
|
* 0x002e - 0x002f....Maybe Super I/O
|
|
* 0x0040 - 0x0043....Timer
|
|
* 0x004e - 0x004f....Maybe Super I/O
|
|
* 0x0050 - 0x0053....Timer aliases
|
|
* 0x0061.............NMI_SC
|
|
* 0x0070.............NMI_EN (readable in alternative access mode)
|
|
* 0x0070 - 0x0077....RTC
|
|
* 0x0080 - 0x008f....ISA DMA
|
|
* 0x0090 ~ 0x009f....ISA DMA aliases
|
|
* 0x0092.............Fast A20 and Init
|
|
* 0x00a0 ~ 0x00bd....PIC
|
|
* 0x00b2 - 0x00b3....APM
|
|
* 0x00c0 ~ 0x00de....ISA DMA
|
|
* 0x00c1 ~ 0x00df....ISA DMA aliases
|
|
* 0x00f0.............Coprocessor Error
|
|
* (0x0400-0x041f)....SMBus (SMBUS_IO_BASE, during raminit)
|
|
* 0x04d0 - 0x04d1....PIC
|
|
* 0x0500 - 0x057f....PM (DEFAULT_PMBASE)
|
|
* 0x0580 - 0x05bf....SB GPIO (DEFAULT_GPIOBASE)
|
|
* 0x05c0 - 0x05ff....SB GPIO cont. (mobile only)
|
|
* 0x0cf8 - 0x0cff....PCI
|
|
* 0x0cf9.............Reset Control
|
|
*/
|
|
|
|
struct resource *res;
|
|
|
|
/* Get the normal PCI resources of this device. */
|
|
pci_dev_read_resources(dev);
|
|
|
|
/* Add an extra subtractive resource for both memory and I/O. */
|
|
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
|
|
res->base = 0;
|
|
res->size = 0x1000;
|
|
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
|
|
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
|
|
|
|
res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
|
|
res->base = 0xff800000;
|
|
res->size = 0x00800000; /* 8 MB for flash */
|
|
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
|
|
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
|
|
|
|
res = new_resource(dev, 3); /* IOAPIC */
|
|
res->base = IO_APIC_ADDR;
|
|
res->size = 0x00001000;
|
|
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
|
|
}
|
|
|
|
static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
|
|
{
|
|
if (!vendor || !device) {
|
|
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
|
|
pci_read_config32(dev, PCI_VENDOR_ID));
|
|
} else {
|
|
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
|
|
((device & 0xffff) << 16) | (vendor & 0xffff));
|
|
}
|
|
}
|
|
|
|
static struct pci_operations pci_ops = {
|
|
.set_subsystem = set_subsystem,
|
|
};
|
|
|
|
static struct device_operations device_ops = {
|
|
.read_resources = i82801ix_lpc_read_resources,
|
|
.set_resources = pci_dev_set_resources,
|
|
.enable_resources = pci_dev_enable_resources,
|
|
.init = lpc_init,
|
|
.scan_bus = scan_static_bus,
|
|
.ops_pci = &pci_ops,
|
|
};
|
|
|
|
static const unsigned short pci_device_ids[] = {
|
|
0x2912, /* ICH9DH */
|
|
0x2914, /* ICH9DO */
|
|
0x2916, /* ICH9R */
|
|
0x2918, /* ICH9 */
|
|
0x2917, /* ICH9M-E */
|
|
0x2919, /* ICH9M */
|
|
0
|
|
};
|
|
|
|
static const struct pci_driver ich9_lpc __pci_driver = {
|
|
.ops = &device_ops,
|
|
.vendor = PCI_VENDOR_ID_INTEL,
|
|
.devices = pci_device_ids,
|
|
};
|
|
|