81ef9c21da
Add SOC_INTEL_COMMON_PCH_LOCKDOWN and PMC_GLOBAL_RESET_ENABLE_LOCK to meet device security requirements. LOCKDOWN has dependencies on SOC_INTEL_COMMON_PCH_BASE and several other common block devices. Add COMMON_PCH_BASE and COMMON_PCH_SERVER to pick up LOCKDOWN and the dependencies. COMMON_PCH_SERVER adds the following common devices that were not previously included by XEON_SP: SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG SOC_INTEL_COMMON_BLOCK_CSE SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG SOC_INTEL_COMMON_BLOCK_ITSS SOC_INTEL_COMMON_PCH_LOCKDOWN SOC_INTEL_COMMON_BLOCK_SATA SOC_INTEL_COMMON_BLOCK_SMBUS SOC_INTEL_COMMON_BLOCK_XHCI Change-Id: Iab97123e487f4f13f874f364a9c51723d234d4f0 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
22 lines
843 B
Makefile
22 lines
843 B
Makefile
## SPDX-License-Identifier: GPL-2.0-or-later
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ifeq ($(CONFIG_XEON_SP_COMMON_BASE),y)
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subdirs-$(CONFIG_SOC_INTEL_SKYLAKE_SP) += skx
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subdirs-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += cpx
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bootblock-y += bootblock.c spi.c lpc.c gpio.c pch.c
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romstage-y += romstage.c reset.c util.c spi.c gpio.c pmutil.c memmap.c
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romstage-y += ../../../cpu/intel/car/romstage.c
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ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c ramstage.c chip_common.c
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ramstage-y += memmap.c pch.c lockdown.c
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ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c
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ramstage-$(CONFIG_HAVE_ACPI_TABLES) += nb_acpi.c acpi.c
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ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c pmc.c
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postcar-y += spi.c
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CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/include
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CPPFLAGS_common += -I$(CONFIG_FSP_HEADER_PATH)
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endif ## XEON_SP_COMMON_BASE
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