coreboot-kgpe-d16/src/soc
Aaron Durbin 6f9947a3ec baytrail: enable caching and prefetching in spi controller
The default mode of the SPI controller has prefetching disabled.
That obviously has a performance impact. Enable both caching
and prefetching to make booting faster. This has a significant
impact on streaming data out of SPI.

BUG=chrome-os-partner:24085
BRANCH=None
TEST=Built and booted rambi. Payload loading step went from ~285ms
     to ~54ms.

Change-Id: I065cf44e1de7dcefc49aa9ea9ad0204929ab26f4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177220
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4976
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07 22:06:03 +02:00
..
intel baytrail: enable caching and prefetching in spi controller 2014-05-07 22:06:03 +02:00
Kconfig Move ARCH_* from board/Kconfig to cpu or soc Kconfig. 2014-05-03 00:25:20 +02:00
Makefile.inc baytrail: add initial support 2014-01-31 16:36:59 +01:00