coreboot-kgpe-d16/src/mainboard/asus/a8n_e/Kconfig
Stefan Reinauer 704b59662d We call this cache as ram everywhere, so let's call it the same in Kconfig
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5756 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-30 17:53:13 +00:00

83 lines
1.2 KiB
Text

if BOARD_ASUS_A8N_E
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
select CPU_AMD_SOCKET_939
select NORTHBRIDGE_AMD_AMDK8
select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
select SOUTHBRIDGE_NVIDIA_CK804
select SUPERIO_ITE_IT8712F
select HAVE_BUS_CONFIG
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select CACHE_AS_RAM
select HAVE_HARD_RESET
select BOARD_ROMSIZE_KB_512
config MAINBOARD_DIR
string
default asus/a8n_e
config DCACHE_RAM_BASE
hex
default 0xcf000
config DCACHE_RAM_SIZE
hex
default 0x01000
config APIC_ID_OFFSET
hex
default 0x0
config MEM_TRAIN_SEQ
int
default 2
config SB_HT_CHAIN_ON_BUS0
int
default 2
config MAINBOARD_PART_NUMBER
string
default "A8N-E"
config HW_MEM_HOLE_SIZEK
hex
default 0x100000
config MAX_CPUS
int
default 2
config MAX_PHYSICAL_CPUS
int
default 1
config HT_CHAIN_END_UNITID_BASE
hex
default 0x20
config HT_CHAIN_UNITID_BASE
hex
default 0x0
config SB_HT_CHAIN_ON_BUS0
int
default 2
config IRQ_SLOT_COUNT
int
default 13
config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
hex
default 0x1043
config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
hex
default 0x815a
endif # BOARD_ASUS_A8N_E