coreboot-kgpe-d16/src/mainboard/winent/pl6064/Kconfig
Stefan Reinauer 704b59662d We call this cache as ram everywhere, so let's call it the same in Kconfig
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5756 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-30 17:53:13 +00:00

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if BOARD_WINENT_PL6064
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
select CPU_AMD_LX
select NORTHBRIDGE_AMD_LX
select SOUTHBRIDGE_AMD_CS5536
select SUPERIO_WINBOND_W83627HF
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC
select CACHE_AS_RAM
select BOARD_ROMSIZE_KB_512
config MAINBOARD_DIR
string
default winent/pl6064
config MAINBOARD_PART_NUMBER
string
default "PL6064"
config IRQ_SLOT_COUNT
int
default 7
config RAMBASE
hex
default 0x4000
endif # BOARD_WINENT_PL6064