Felix Held 70f1af8934 soc/amd/cezanne: remove UART2/3 AOAC device offsets ... UART2 and UART3 don't exist on Cezanne which now has been verified, so remove the corresponding AOAC offsets. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I67755bd34df3a835cc39929bdc24f711d158b3a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>		2021-02-03 19:59:54 +00:00
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cezanne	soc/amd/cezanne: remove UART2/3 AOAC device offsets	2021-02-03 19:59:54 +00:00
common	src: Remove unused <cbmem.h>	2021-02-03 08:56:35 +00:00
picasso	soc/amd/picasso: clean up and re-sort UPD table	2021-02-03 17:27:30 +00:00
stoneyridge	soc/amd: Drop PCNT from GNVS	2021-02-01 08:54:23 +00:00
Kconfig	soc/amd: rename common Kconfig and use wildcard for SoC-specific Kconfig	2020-11-19 14:29:14 +00:00