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coreboot-kgpe-d16/src/arch/riscv
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Jonathan Neuschäfer 710566093a riscv-spike: Move coreboot to 0x80000000 (2GiB) 
This is where the RAM is (now), on RISC-V.

We need to put coreboot.rom in RAM because Spike (at the moment) only
supports loading code into the RAM, not into the boot ROM.

Change-Id: I6c9b7cffe5fa414825491ee4ac0d2dad59a2d75c
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15149
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21 00:11:49 +02:00
..
include arch/riscv: copy read/write8/16/32 from x86 2016-06-12 12:40:51 +02:00
boot.c die() when attempting to use bounce buffer on non-i386. 2016-02-22 18:38:48 +01:00
bootblock.S riscv-spike: Move coreboot to 0x80000000 (2GiB) 2016-06-21 00:11:49 +02:00
bootblock_simple.c arm/arm64: Generalize bootblock C entry point 2015-11-11 05:08:07 +01:00
id.ld arch/riscv: Add missing license headers 2016-01-18 02:14:03 +01:00
Kconfig console: Simplify bootblock console Kconfig selection logic 2016-01-21 05:37:27 +01:00
Makefile.inc arch/riscv: Compile with -mcmodel=medany 2016-06-12 12:42:32 +02:00
misc.c arch/riscv: Add missing license headers 2016-01-18 02:14:03 +01:00
prologue.inc tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
rom_media.c tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
stages.c arch: remove stage_exit() 2016-02-11 23:12:06 +01:00
tables.c lib: add common write_tables() implementation 2016-04-21 20:49:05 +02:00
trap_handler.c RISC-V: Add more debug info to debug printks 2016-02-19 05:42:52 +01:00
trap_util.S arch/riscv/trap_util.S: Use "li" pseudo-instruction to load a constant 2016-06-12 12:31:06 +02:00
virtual_memory.c tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00