76c3700f02
The Haswell parts use a PCH code named Lynx Point (Series 8). Therefore, the southbridge support is included as well. The basis for this code is the Sandybridge code. Management Engine, IRQ routing, and ACPI still requires more attention, but this is a good starting point. This code partially gets up through the romstage just before training memory on a Haswell reference board. Change-Id: If572d6c21ca051b486b82a924ca0ffe05c4d0ad4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2616 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
17 lines
891 B
Makefile
17 lines
891 B
Makefile
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_E7501) += e7501
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_E7505) += e7505
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_E7520) += e7520
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_E7525) += e7525
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I3100) += i3100
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I440BX) += i440bx
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I440LX) += i440lx
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I82810) += i82810
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I82830) += i82830
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I855) += i855
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945) += i945
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_GM45) += gm45
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SCH) += sch
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I5000) += i5000
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += sandybridge
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += sandybridge
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell
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