36a67e1f3c
This patch selects the fmd files based on config
BOARD_GOOGLE_BASEBOARD_HATCH and also renames them to
add the baseboard name and layout size tags.
BUG=b:154561163
TEST=Built hatch variants and verified that they select the
right fmd files.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I5d99ae28cc972ffa635adf100b756c36e168a8f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
47 lines
1.3 KiB
Text
47 lines
1.3 KiB
Text
FLASH@0xfe000000 0x2000000 {
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SI_ALL@0x0 0x400000 {
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SI_DESC@0x0 0x1000
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SI_ME@0x1000 0x3ff000
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}
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SI_BIOS@0x400000 0x1c00000 {
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# Place RW_LEGACY at the start of BIOS region such that the rest
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# of BIOS regions start at 16MiB boundary. Since this is a 32MiB
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# SPI flash only the top 16MiB actually gets memory mapped.
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RW_LEGACY(CBFS)@0x0 0x1000000
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RW_SECTION_A@0x1000000 0x3e0000 {
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VBLOCK_A@0x0 0x10000
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FW_MAIN_A(CBFS)@0x10000 0x3cffc0
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RW_FWID_A@0x3dffc0 0x40
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}
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RW_SECTION_B@0x13e0000 0x3e0000 {
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VBLOCK_B@0x0 0x10000
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FW_MAIN_B(CBFS)@0x10000 0x3cffc0
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RW_FWID_B@0x3dffc0 0x40
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}
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RW_MISC@0x17c0000 0x40000 {
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UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 {
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RECOVERY_MRC_CACHE@0x0 0x10000
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RW_MRC_CACHE@0x10000 0x20000
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}
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RW_ELOG(PRESERVE)@0x30000 0x4000
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RW_SHARED@0x34000 0x4000 {
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SHARED_DATA@0x0 0x2000
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VBLOCK_DEV@0x2000 0x2000
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}
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RW_VPD(PRESERVE)@0x38000 0x2000
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RW_NVRAM(PRESERVE)@0x3a000 0x6000
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}
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# Make WP_RO region align with SPI vendor
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# memory protected range specification.
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WP_RO@0x1800000 0x400000 {
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RO_VPD(PRESERVE)@0x0 0x4000
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RO_SECTION@0x4000 0x3fc000 {
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FMAP@0x0 0x800
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RO_FRID@0x800 0x40
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RO_FRID_PAD@0x840 0x7c0
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GBB@0x1000 0x3000
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COREBOOT(CBFS)@0x4000 0x3f8000
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}
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}
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}
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}
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