72a8e5e751
These binaries were being added to CBFS using hexadecimal values instead of the CBFS binary type names. The same value was being used in different places for different things. For example, the value 0xAB is used for SPDs, MRC & FSP binaries. This patch uses CBFS type names instead of hex values everywhere a hex value was previously used. Change-Id: Id5ac74c3095eb02a2b39d25104a25933304a8389 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/8978 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
130 lines
4.1 KiB
Makefile
130 lines
4.1 KiB
Makefile
subdirs-y += bootblock
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subdirs-y += microcode
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subdirs-y += romstage
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subdirs-y += ../common
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subdirs-y += ../../../cpu/x86/lapic
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subdirs-y += ../../../cpu/x86/mtrr
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subdirs-y += ../../../cpu/x86/smm
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subdirs-y += ../../../cpu/x86/tsc
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subdirs-y += ../../../cpu/intel/microcode
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subdirs-y += ../../../cpu/intel/turbo
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ramstage-y += acpi.c
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ramstage-y += adsp.c
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ramstage-y += chip.c
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ramstage-y += cpu.c
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ramstage-y += cpu_info.c
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smm-y += cpu_info.c
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ramstage-$(CONFIG_ELOG) += elog.c
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ramstage-y += finalize.c
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ramstage-y += gpio.c
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romstage-y += gpio.c
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smm-y += gpio.c
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ramstage-y += hda.c
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ramstage-y += igd.c
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ramstage-y += iobp.c
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romstage-y += iobp.c
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ramstage-y += lpc.c
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ramstage-y += me.c
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ramstage-y += me_status.c
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romstage-y += me_status.c
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ramstage-y += memmap.c
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romstage-y += memmap.c
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ramstage-y += minihd.c
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ramstage-y += monotonic_timer.c
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ramstage-y += pch.c
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romstage-y += pch.c
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ramstage-y += pcie.c
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ramstage-y += pei_data.c
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romstage-y += pei_data.c
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ramstage-y += pmutil.c
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romstage-y += pmutil.c
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smm-y += pmutil.c
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ramstage-y += ramstage.c
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ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c
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ramstage-y += reset.c
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romstage-y += reset.c
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ramstage-y += sata.c
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ramstage-y += serialio.c
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ramstage-y += smbus.c
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ramstage-y += smbus_common.c
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romstage-y += smbus_common.c
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ramstage-y += smi.c
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smm-y += smihandler.c
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ramstage-y += smmrelocate.c
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ramstage-y += spi.c
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smm-$(CONFIG_SPI_FLASH_SMM) += spi.c
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ramstage-y += stage_cache.c
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romstage-y += stage_cache.c
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ramstage-y += systemagent.c
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ramstage-y += tsc_freq.c
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romstage-y += tsc_freq.c
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smm-y += tsc_freq.c
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ramstage-y += ehci.c
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ramstage-y += xhci.c
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smm-y += xhci.c
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ifeq ($(CONFIG_USBDEBUG),y)
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ramstage-y += usbdebug.c
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romstage-y += usbdebug.c
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smm-y += usbdebug.c
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endif
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CPPFLAGS_common += -Isrc/soc/intel/broadwell/
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# Run an intermediate step when producing coreboot.rom
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# that adds additional components to the final firmware
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# image outside of CBFS
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INTERMEDIATE := broadwell_add_me
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ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
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IFD_BIN_PATH := $(objgenerated)/ifdfake.bin
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IFD_SECTIONS := $(addprefix -b ,$(CONFIG_IFD_BIOS_SECTION:"%"=%)) \
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$(addprefix -m ,$(CONFIG_IFD_ME_SECTION:"%"=%)) \
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$(addprefix -p ,$(CONFIG_IFD_PLATFORM_SECTION:"%"=%))
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else
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IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH)
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endif
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broadwell_add_me: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE)
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ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
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printf "\n** WARNING **\n"
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printf "Coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n"
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printf "Never write a complete coreboot.rom with a fake IFD to your board's\n"
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printf "flash ROM! Make sure that you only write valid flash regions.\n\n"
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printf " IFDFAKE Building a fake Intel Firmware Descriptor\n"
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$(IFDFAKE) $(IFD_SECTIONS) $(IFD_BIN_PATH)
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endif
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printf " DD Adding Intel Firmware Descriptor\n"
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dd if=$(IFD_BIN_PATH) \
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of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
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ifeq ($(CONFIG_HAVE_ME_BIN),y)
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printf " IFDTOOL me.bin -> coreboot.pre\n"
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$(objutil)/ifdtool/ifdtool \
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-i ME:$(CONFIG_ME_BIN_PATH) \
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$(obj)/coreboot.pre
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mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
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ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y)
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printf " IFDTOOL Locking Management Engine\n"
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$(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre
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mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
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else
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printf " IFDTOOL Unlocking Management Engine\n"
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$(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre
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mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
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endif
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endif
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PHONY += broadwell_add_me
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# If an MRC file is an ELF file determine the entry address and first loadable
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# section offset in the file. Subtract the offset from the entry address to
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# determine the final location.
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mrcelfoffset = $(shell $(READELF_x86_32) -S -W $(CONFIG_MRC_FILE) | sed -e 's/\[ /[0/' | awk '$$3 ~ /PROGBITS/ { print "0x"$$5; exit }' )
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mrcelfentry = $(shell $(READELF_x86_32) -h -W $(CONFIG_MRC_FILE) | grep 'Entry point address' | awk '{print $$NF }')
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# Add memory reference code blob.
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cbfs-files-$(CONFIG_HAVE_MRC) += mrc.bin
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mrc.bin-file := $(call strip_quotes,$(CONFIG_MRC_FILE))
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mrc.bin-position := $(if $(findstring elf,$(CONFIG_MRC_FILE)),$(shell printf "0x%x" $$(( $(mrcelfentry) - $(mrcelfoffset) )) ),$(CONFIG_MRC_BIN_ADDRESS))
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mrc.bin-type := mrc
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