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Sridhar Siricilla 7301cfac60 soc/intel/common: Order the different types of cores based on APIC IDs 
Currently coreboot presents the BSP core first, then efficient cores and
Performance cores as indicated below:

```
/sys/devices/system/cpu/cpu0/topology/thread_siblings_list:0-1
/sys/devices/system/cpu/cpu4/topology/thread_siblings_list:4
/sys/devices/system/cpu/cpu5/topology/thread_siblings_list:5
/sys/devices/system/cpu/cpu6/topology/thread_siblings_list:6
/sys/devices/system/cpu/cpu7/topology/thread_siblings_list:7
/sys/devices/system/cpu/cpu1/topology/thread_siblings_list:0-1
/sys/devices/system/cpu/cpu2/topology/thread_siblings_list:2-3
/sys/devices/system/cpu/cpu3/topology/thread_siblings_list:2-3

```
Existing code presents mix of different cores to OS and causes CPU load
balancing and power/performance impact. So, the patch fixes this
disorder by ordering the Performance cores first, compute die efficient
cores next, and finally SOC efficient cores if they are present. This
is done to run the media applications in a power efficient manner,
please refer the ChromeOS patches for details:
https://chromium-review.googlesource.com/c/chromiumos/platform2/+/3963893

BUG=b:262886449
TEST=Verified the code on Rex system

After the fix:

```
/sys/devices/system/cpu/cpu0/topology/thread_siblings_list:0-1
/sys/devices/system/cpu/cpu1/topology/thread_siblings_list:0-1
/sys/devices/system/cpu/cpu2/topology/thread_siblings_list:2-3
/sys/devices/system/cpu/cpu3/topology/thread_siblings_list:2-3
/sys/devices/system/cpu/cpu4/topology/thread_siblings_list:4
/sys/devices/system/cpu/cpu5/topology/thread_siblings_list:5
/sys/devices/system/cpu/cpu6/topology/thread_siblings_list:6
/sys/devices/system/cpu/cpu7/topology/thread_siblings_list:7
```

Change-Id: I21487a5eb0439ea0cb5976787d1769ee94777469
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2023-04-07 09:59:52 +00:00
..
amd amd/mendocino/root_complex: Restrict DPTC to 15W boards 2023-04-06 18:00:42 +00:00
cavium treewide: Remove duplicated include <device/pci.h> 2023-02-01 03:03:34 +00:00
example/min86
intel soc/intel/common: Order the different types of cores based on APIC IDs 2023-04-07 09:59:52 +00:00
mediatek soc/mediatek/mt8186: Shut down PMIC on power key long press 2023-03-15 10:30:17 +00:00
nvidia treewide: stop calling custom TPM log "TCPA" 2023-01-11 16:00:55 +00:00
qualcomm qualcomm/common: Pass FMAX_LIMIT flag for Lazor board to QcLib 2023-03-17 00:34:08 +00:00
rockchip
samsung treewide: Fix old-style declarations 2023-01-17 04:23:49 +00:00
sifive/fu540
ti
ucb/riscv