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This patch refactors the existing MRC cache storing logic, which was spread between the ROM and RAM stages, into a single early MRC cache store stage. The only exception is when SoC user selects FSP_NVS_DATA_POST_SILICON_INIT to store MRC cache from ramstage (after FSP-S). It reverts all the boot-state logic previously used to locate and store MRC cache from NVS HOB into NVS because majority of the platform can potentially use the early MRC cache store with improved memory caching at the pre-RAM phase (with the ramtop implementation). The only exception is the Xeon SP platform, which currently locates the MRC cache post in FSP-S (at ramstage). Therefore, this patch provides an API to the FSP 2.x silicon init code to perform late storing of the MRC cache. In majority cases the updated logic, the romstage (post FSP-M) will attempt to save the MRC cache. Platform that selects FSP_NVS_DATA_POST_SILICON_INIT config performs the same operation post FSP-S. Depending on whether the MRC_STASH_TO_CBMEM config is enabled, the MRC cache will either be written directly to NVRAM at the romstage or stashed into CBMEM for a late NVRAM write at ramstage. Below table captures the change in the boot state w/ and w/o this patch for storing the MRC cache. Overall the goal is to ensure the platform behavior is remain unchanged before and after this patch. w/o this patch: | | Save MRC | Finalize | Lock the | | | Cache | MRC Cache | Boot Medium | +-----------+----------------+----------------+----------------+ | MRC_WRITE | BS_OS_RESUME | BS_OS_RESUME | BS_ON_RESUME | | NV_LATE | CHECK_ENTRY | CHECK_ENTRY | CHECK_EXIT | +-----------+----------------+----------------+----------------+ | MRC_STASH | BS_DEV | BS_DEV | BS_DEV | | TO_CBMEM | ENUMERATE_EXIT | ENUMERATE_EXIT | RESOURCES_ENTRY| +-----------+----------------+----------------+----------------+ | FSP_NVS | BS_DEV_INIT | BS_DEV | BS_DEV | | DATA_POST | CHIPS_EXIT | ENUMERATE_EXIT | RESOURCES_ENTRY| | SILICON | | | | | INIT | | | | +-----------+----------------+----------------+----------------+ | Platform | BS_PRE | BS_DEV | BS_DEV | | w/o above | DEVICE_ENTRY | ENUMERATE_EXIT | ENUMERATE_ENTRY| | config | | | | | (FSP 2.0 | | | | | platforms | | | | w/ this patch: | | Save MRC | Finalize | Lock the | | | Cache | MRC Cache | Boot Medium | +-----------+----------------+----------------+----------------+ | MRC_WRITE | BS_OS_RESUME | BS_OS_RESUME | BS_ON_RESUME | | NV_LATE | CHECK_ENTRY | CHECK_ENTRY | CHECK_EXIT | +-----------+----------------+----------------+----------------+ | MRC_STASH | BS_DEV | BS_DEV | BS_DEV | | TO_CBMEM | ENUMERATE_EXIT | ENUMERATE_EXIT | RESOURCES_ENTRY| +-----------+----------------+----------------+----------------+ | FSP_NVS | Post FSP-S | BS_DEV | BS_DEV | | DATA_POST | (ramstage) | ENUMERATE_EXIT | RESOURCES_ENTRY| | SILICON | | | | | INIT | | | | +-----------+----------------+----------------+----------------+ | Platform | Post FSP-M | BS_DEV | BS_DEV | | w/o above | (romstage) | ENUMERATE_EXIT | ENUMERATE_ENTRY| | config | | | | | (FSP 2.0 | | | | | platforms | | | | BUG=b:296704537 TEST=Able to build and boot google/rex without any boot time impact. Change-Id: Id1e91d25916594f59d1e467a142f5042c6138b51 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77556 Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
56 lines
1.6 KiB
C
56 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _COMMON_MRC_CACHE_H_
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#define _COMMON_MRC_CACHE_H_
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#include <stddef.h>
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#include <stdint.h>
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#include <commonlib/region.h>
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enum {
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MRC_TRAINING_DATA,
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MRC_VARIABLE_DATA,
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};
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/*
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* It's up to the caller to decide when to retrieve and stash data. There is
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* differentiation on recovery mode CONFIG(HAS_RECOVERY_MRC_CACHE), but that's
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* only for locating where to retrieve and save the data. If a platform doesn't
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* want to update the data then it shouldn't stash the data for saving.
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* Similarly, if the platform doesn't need the data for booting because of a
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* policy don't request the data.
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*/
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/* Get and stash data for saving provided the type passed in. */
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/**
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* mrc_cache_load_current
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*
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* Fill in the buffer with the latest slot data. This will be a
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* common entry point for ARM platforms. Returns < 0 on error, size
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* of the returned data on success.
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*/
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ssize_t mrc_cache_load_current(int type, uint32_t version, void *buffer,
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size_t buffer_size);
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/**
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* mrc_cache_mmap_leak
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*
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* Return a pointer to a buffer with the latest slot data. An mmap
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* will be executed (without a matching unmap). This will be a common
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* entry point for platforms where mmap is considered a noop, like x86
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*/
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void *mrc_cache_current_mmap_leak(int type, uint32_t version,
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size_t *data_size);
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/**
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* Returns < 0 on error, 0 on success.
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*/
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int mrc_cache_stash_data(int type, uint32_t version, const void *data,
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size_t size);
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/**
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* API to locate the FSP Non-Volatile Storage Data (aka memory training data)
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* and store into the NVS.
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*/
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void save_memory_training_data(void);
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#endif /* _COMMON_MRC_CACHE_H_ */
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