6350a2e43f
Change-Id: Ib00a9b2feb723d46642d86b2706728bbca7dd68d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16616 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
55 lines
1.7 KiB
C
55 lines
1.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
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* Copyright (C) 2010 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <arch/io.h>
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#include "southbridge/via/vt8237r/vt8237r.h"
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u32 vt8237_ide_80pin_detect(struct device *dev)
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{
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device_t lpc_dev;
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u16 acpi_io_base;
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u32 gpio_in;
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u32 res;
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lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
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PCI_DEVICE_ID_VIA_VT8237R_LPC, 0);
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if (!lpc_dev)
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return 0;
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acpi_io_base = pci_read_config16(lpc_dev, 0x88) & ~1;
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if (!acpi_io_base)
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return 0;
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/* select function GPIO29 for pin AB9 */
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pci_write_config8(lpc_dev, 0xe5, pci_read_config8(lpc_dev, 0xe5) | 0x08);
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gpio_in = inl(acpi_io_base + 0x48);
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/* bit 29 for primary port, clear if unconnected or 80-pin cable */
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res = gpio_in & (1 << 29) ? 0 : VT8237R_IDE0_80PIN_CABLE;
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/* bit 8 for secondary port, clear if unconnected or 80-pin cable */
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res |= gpio_in & (1 << 8) ? 0 : VT8237R_IDE1_80PIN_CABLE;
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printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "primary",
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res & VT8237R_IDE0_80PIN_CABLE ? 80 : 40);
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printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "secondary",
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res & VT8237R_IDE1_80PIN_CABLE ? 80 : 40);
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return res;
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}
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