8d0e88db34
Change-Id: I2fe8d8388cb96e42af4f9be251a41cceeb2e4710 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27042 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
40 lines
1.3 KiB
C
40 lines
1.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ_H
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#define SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ_H
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/*
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* The DnnIR registers use common RCBA offsets across these chipsets:
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* bd82x6x, i82801, i89xx, ibexpeak, lynxpoint
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*
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* However not all registers are in use on all of these.
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*/
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#define D31IR 0x3140 /* 16bit */
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#define D30IR 0x3142 /* 16bit */
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#define D29IR 0x3144 /* 16bit */
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#define D28IR 0x3146 /* 16bit */
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#define D27IR 0x3148 /* 16bit */
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#define D26IR 0x314c /* 16bit */
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#define D25IR 0x3150 /* 16bit */
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#define D23IR 0x3158 /* 16bit */
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#define D22IR 0x315c /* 16bit */
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#define D21IR 0x3164 /* 16bit */
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#define D20IR 0x3160 /* 16bit */
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#define D19IR 0x3168 /* 16bit */
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#endif /* SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ_H */
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