739df1b2c2
BUG=chrome-os-partner:29778 TEST=Build coreboot Change-Id: I877b4bf741f45f6cfd032ad5018a60e8a1453622 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 640da5ad5597803c62d9374a1a48832003077723 Original-Change-Id: I805d93e94f73418099f47d235ca920a91b4b2bfb Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209469 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Tested-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8867 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
143 lines
4 KiB
C
143 lines
4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Rockchip Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <arch/cache.h>
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#include <delay.h>
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#include <edid.h>
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#include <vbe.h>
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#include <boot/coreboot_tables.h>
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#include <device/i2c.h>
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#include <soc/rockchip/rk3288/gpio.h>
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#include <soc/rockchip/rk3288/soc.h>
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#include <soc/rockchip/rk3288/pmu.h>
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#include <soc/rockchip/rk3288/clock.h>
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#include <soc/rockchip/rk3288/spi.h>
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#include "pmic.h"
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#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20)
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#define DRAM_SIZE CONFIG_DRAM_SIZE_MB
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#define DRAM_END (DRAM_START + DRAM_SIZE)
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static void setup_gpio(void)
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{
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/*SOC and TPM reset GPIO, active high.*/
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gpio_output((gpio_t){.port = 0, .bank = GPIO_B, .idx = 2}, 0);
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/* Configure GPIO for lcd_bl_en */
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gpio_output((gpio_t){.port = 7, .bank = GPIO_A, .idx = 2}, 1);
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/*Configure backlight PWM 100% brightness*/
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gpio_output((gpio_t){.port = 7, .bank = GPIO_A, .idx = 0}, 0);
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/* Configure GPIO for lcd_en */
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gpio_output((gpio_t){.port = 7, .bank = GPIO_B, .idx = 7}, 1);
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}
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static void setup_iomux(void)
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{
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/*i2c0 for pmic*/
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setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
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setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
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/*i2c1 for tpm*/
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writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
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/*i2c2 for codec*/
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writel(IOMUX_I2C2, &rk3288_grf->iomux_i2c2);
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writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0);
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writel(IOMUX_I2S, &rk3288_grf->iomux_i2s);
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writel(IOMUX_I2SCLK, &rk3288_grf->iomux_i2sclk);
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writel(IOMUX_LCDC, &rk3288_grf->iomux_lcdc);
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writel(IOMUX_SDMMC0, &rk3288_grf->iomux_sdmmc0);
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writel(IOMUX_EMMCDATA, &rk3288_grf->iomux_emmcdata);
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writel(IOMUX_EMMCPWREN, &rk3288_grf->iomux_emmcpwren);
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writel(IOMUX_EMMCCMD, &rk3288_grf->iomux_emmccmd);
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}
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static void setup_usb_poweron(void)
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{
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/* Configure GPIO for usb1_pwr_en */
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gpio_output((gpio_t){.port = 0, .bank = GPIO_B, .idx = 3}, 1);
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/* Configure GPIO for usb2_pwr_en */
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gpio_output((gpio_t){.port = 0, .bank = GPIO_B, .idx = 4}, 1);
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/* Configure GPIO for 5v_drv */
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gpio_output((gpio_t){.port = 7, .bank = GPIO_B, .idx = 3}, 1);
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}
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static void configure_sdmmc(void)
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{
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/* Configure GPIO for sd_en */
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gpio_output((gpio_t){.port = 7, .bank = GPIO_C, .idx = 5}, 1);
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/* Configure GPIO for sd_detec */
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gpio_input_pullup((gpio_t){.port = 7, .bank = GPIO_A, .idx = 5});
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/*use sdmmc0 io, disable JTAG function*/
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writel(RK_CLRBITS(1 << 12), &rk3288_grf->soc_con0);
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}
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static void configure_emmc(void)
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{
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/* Configure GPIO for emmc_pwrctrl */
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gpio_output((gpio_t){.port = 7, .bank = GPIO_B, .idx = 4}, 1);
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}
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static void configure_i2s(void)
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{
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/*AUDIO IO domain 1.8V voltage selection*/
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writel(RK_SETBITS(1 << 6), &rk3288_grf->io_vsel);
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rkclk_configure_i2s(12288000);
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}
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static void mainboard_init(device_t dev)
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{
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setup_iomux();
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pmic_init(0);
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setup_gpio();
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setup_usb_poweron();
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configure_sdmmc();
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configure_emmc();
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configure_i2s();
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rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS);
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}
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static void mainboard_enable(device_t dev)
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{
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dev->ops->init = &mainboard_init;
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}
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struct chip_operations mainboard_ops = {
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.enable_dev = mainboard_enable,
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};
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void lb_board(struct lb_header *header)
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{
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struct lb_range *dma;
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dma = (struct lb_range *)lb_new_record(header);
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dma->tag = LB_TAB_DMA;
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dma->size = sizeof(*dma);
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dma->range_start = CONFIG_DRAM_DMA_START;
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dma->range_size = CONFIG_DRAM_DMA_SIZE;
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}
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