742c6fedbd
Move funtions callbacks used to override FSP upd values to separate files. This serves as a base change for SoCs for which FSP is still under development, and hence the FSP header files are not available yet and in turn the UPDs cannot be referred. These newer SoCs will implement empty callbacks. The code will compile with basic header files which only include the architectural FSP structures. This allows plugging in these separate files for compilation in an environment where FSP header files are available. The fact is, FSP header files are not released externally until PRQ. However the teams at intel and some partners have access to the development version of these files. This code refactor helps to continue development on the pre-PRQ silicons and submit related code to coreboot.org. BUG=None BRANCH=None TEST=Build for cnlrvp Change-Id: Iffadc57f6986e688aa1bbe4e5444d105386ad92e Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/28661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
127 lines
3.7 KiB
Makefile
127 lines
3.7 KiB
Makefile
ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE),y)
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subdirs-y += romstage
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subdirs-y += ../../../cpu/intel/microcode
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subdirs-y += ../../../cpu/intel/turbo
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subdirs-y += ../../../cpu/x86/lapic
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subdirs-y += ../../../cpu/x86/mtrr
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subdirs-y += ../../../cpu/x86/smm
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subdirs-y += ../../../cpu/x86/tsc
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bootblock-y += bootblock/bootblock.c
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bootblock-y += bootblock/cpu.c
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bootblock-y += bootblock/pch.c
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bootblock-y += pmutil.c
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bootblock-y += bootblock/report_platform.c
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bootblock-y += gpio.c
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bootblock-y += gspi.c
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bootblock-y += i2c.c
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bootblock-y += memmap.c
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bootblock-y += spi.c
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bootblock-y += lpc.c
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bootblock-y += p2sb.c
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bootblock-$(CONFIG_UART_DEBUG) += uart.c
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romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_MEMCFG_INIT) += cnl_memcfg_init.c
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romstage-y += gpio.c
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romstage-y += gspi.c
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romstage-y += i2c.c
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romstage-y += lpc.c
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romstage-y += memmap.c
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romstage-y += pmutil.c
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romstage-y += reset.c
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romstage-y += spi.c
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romstage-$(CONFIG_UART_DEBUG) += uart.c
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ramstage-y += acpi.c
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ramstage-y += chip.c
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ramstage-y += cpu.c
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ramstage-y += finalize.c
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ramstage-y += fsp_params.c
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ramstage-y += gpio.c
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ramstage-y += graphics.c
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ramstage-y += gspi.c
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ramstage-y += gpio.c
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ramstage-y += i2c.c
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ramstage-y += lockdown.c
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ramstage-y += lpc.c
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ramstage-y += memmap.c
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ramstage-y += nhlt.c
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ramstage-y += p2sb.c
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ramstage-y += pmc.c
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ramstage-y += pmutil.c
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ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
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ramstage-y += smmrelocate.c
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ramstage-y += spi.c
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ramstage-y += systemagent.c
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ramstage-$(CONFIG_UART_DEBUG) += uart.c
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ramstage-y += vr_config.c
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ramstage-y += sd.c
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smm-y += gpio.c
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smm-y += p2sb.c
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smm-y += pmutil.c
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smm-y += smihandler.c
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smm-$(CONFIG_UART_DEBUG) += uart.c
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postcar-y += memmap.c
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postcar-y += pmutil.c
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postcar-y += i2c.c
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postcar-y += gspi.c
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postcar-y += spi.c
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postcar-$(CONFIG_UART_DEBUG) += uart.c
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verstage-y += gspi.c
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verstage-y += i2c.c
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verstage-y += pmutil.c
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verstage-y += spi.c
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verstage-$(CONFIG_UART_DEBUG) += uart.c
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ifeq ($(CONFIG_SOC_INTEL_COFFEELAKE),y)
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CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/coffeelake
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else
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CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/cannonlake
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endif
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CPPFLAGS_common += -I$(src)/soc/intel/cannonlake
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CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include
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# DSP firmware settings files.
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NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/cnl/nhlt-blobs
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DMIC_1CH_48KHZ_16B = dmic-1ch-48khz-16b.bin
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DMIC_2CH_48KHZ_16B = dmic-2ch-48khz-16b.bin
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DMIC_4CH_48KHZ_16B = dmic-4ch-48khz-16b.bin
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MAX98357_RENDER = max98357-render-2ch-48khz-24b.bin
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DA7219_RENDER_CAPTURE = dialog-2ch-48khz-24b.bin
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MAX98373_RENDER_24B = max98373-render-2ch-48khz-24b.bin
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MAX98373_RENDER_16B = max98373-render-2ch-48khz-16b.bin
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cbfs-files-$(CONFIG_NHLT_DMIC_1CH_16B) += $(DMIC_1CH_48KHZ_16B)
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$(DMIC_1CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_1CH_48KHZ_16B)
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$(DMIC_1CH_48KHZ_16B)-type := raw
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cbfs-files-$(CONFIG_NHLT_DMIC_2CH_16B) += $(DMIC_2CH_48KHZ_16B)
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$(DMIC_2CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_2CH_48KHZ_16B)
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$(DMIC_2CH_48KHZ_16B)-type := raw
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cbfs-files-$(CONFIG_NHLT_DMIC_4CH_16B) += $(DMIC_4CH_48KHZ_16B)
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$(DMIC_4CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_4CH_48KHZ_16B)
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$(DMIC_4CH_48KHZ_16B)-type := raw
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cbfs-files-$(CONFIG_NHLT_MAX98357) += $(MAX98357_RENDER)
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$(MAX98357_RENDER)-file := $(NHLT_BLOB_PATH)/$(MAX98357_RENDER)
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$(MAX98357_RENDER)-type := raw
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cbfs-files-$(CONFIG_NHLT_MAX98373) += $(MAX98373_RENDER_16B)
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$(MAX98373_RENDER_16B)-file := $(NHLT_BLOB_PATH)/$(MAX98373_RENDER_16B)
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$(MAX98373_RENDER_16B)-type := raw
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cbfs-files-$(CONFIG_NHLT_MAX98373) += $(MAX98373_RENDER_24B)
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$(MAX98373_RENDER_24B)-file := $(NHLT_BLOB_PATH)/$(MAX98373_RENDER_24B)
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$(MAX98373_RENDER_24B)-type := raw
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cbfs-files-$(CONFIG_NHLT_DA7219) += $(DA7219_RENDER_CAPTURE)
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$(DA7219_RENDER_CAPTURE)-file := $(NHLT_BLOB_PATH)/$(DA7219_RENDER_CAPTURE)
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$(DA7219_RENDER_CAPTURE)-type := raw
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endif
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