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now all have the same parameter order. action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c -S $(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -o $@" The idea behind this parameter order is: - *FLAGS at the beginning. - Use a common set of *FLAGS. - Include files and directories listed afterwards. - nostdinc, nostdlib, no-builtin tell the compiler this is standalone code. - Warnings. They do not influence source or compilation. - Compilation strategy (small) and output mode (asm or binary). - File to be compiled. - Output name. - $(DEBUG_CFLAGS) and -S are only used for asm output. Other changes in this patch: - src/supermicro/h8dme/Config.lb now uses $DEBUG_CFLAGS instead of hardcoding the respective flags. - $DEBUG_CFLAGS was added to asm outputting $CC calls: supermicro/h8dme/Config.lb lippert/roadrunner-lx/Config.lb - $DISTRO_CFLAGS was added to some $CC calls in: iwill/dk8_htx/Config.lb (CAR AP code) supermicro/h8dmr/Config.lb (CAR AP code) supermicro/h8dme/Config.lb (CAR AP code) gigabyte/m57sli/Config.lb (CAR AP code) gigabyte/ga_2761gxdk/Config.lb (CAR AP code) amd/serengeti_cheetah_fam10/Config.lb (everywhere) msi/ms7135/Config.lb (everywhere) nvidia/l1_2pvv/Config.lb (CAR AP code) -$CFLAGS was added to all $CC calls in: amd/db800/Config.lb amd/dbm690t/Config.lb amd/norwich/Config.lb amd/pistachio/Config.lb amd/serengeti_cheetah/Config.lb amd/serengeti_cheetah_fam10/Config.lb arima/hdama/Config.lb artecgroup/dbe61/Config.lb asus/a8n_e/Config.lb asus/a8v-e_se/Config.lb asus/m2v-mx_se/Config.lb broadcom/blast/Config.lb digitallogic/msm800sev/Config.lb gigabyte/ga_2761gxdk/Config.lb gigabyte/m57sli/Config.lb ibm/e325/Config.lb ibm/e326/Config.lb iei/pcisa-lx-800-r10/Config.lb iwill/dk8_htx/Config.lb iwill/dk8s2/Config.lb iwill/dk8x/Config.lb kontron/986lcd-m/Config.lb lippert/roadrunner-lx/Config.lb lippert/spacerunner-lx/Config.lb msi/ms7135/Config.lb msi/ms7260/Config.lb msi/ms9185/Config.lb msi/ms9282/Config.lb newisys/khepri/Config.lb nvidia/l1_2pvv/Config.lb pcengines/alix1c/Config.lb sunw/ultra40/Config.lb supermicro/h8dme/Config.lb supermicro/h8dmr/Config.lb technexion/tim8690/Config.lb tyan/s2735/Config.lb tyan/s2850/Config.lb tyan/s2875/Config.lb tyan/s2880/Config.lb tyan/s2881/Config.lb tyan/s2882/Config.lb tyan/s2885/Config.lb tyan/s2891/Config.lb tyan/s2892/Config.lb tyan/s2895/Config.lb tyan/s2912/Config.lb tyan/s2912_fam10/Config.lb tyan/s4880/Config.lb tyan/s4882/Config.lb - Use $@ wherever appropriate. - Kill that evil CACHE_AS_RAM_AUTO_C variable. - Trailing whitespace fixups on lines which were touched anyway. We now only have 6 remaining different calls to $CC whereas before there were 20. If I am allowed to rename src/mainboard/kontron/986lcd-m/auto.c to src/mainboard/kontron/986lcd-m/cache_as_ram_auto.c, we're down to 4 different calls. If we can decide on the use of $CPU_OPT, we are down to 3 different calls. One additional point I'd like to clear up: if ASSEMBLER_DEBUG makedefine DEBUG_CFLAGS := -g -dA -fverbose-asm end "-dA -fverbose-asm" is only useful for asm output. For these flags, DEBUG_CFLAGS is a total misnomer. What about calling them DEBUG_ASMCFLAGS or somesuch? "-g" should be controllable by a separate switch. It is useful even for object code. The following targets are broken by this patch because they contain implicit declarations, but the error did not trigger due to missing CFLAGS: amd/serengeti_cheetah asus/a8v-e_se asus/m2v-mx_se digitallogic/msm800sev pcengines/alix1c supermicro/h8dme supermicro/h8dmr Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4097 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
284 lines
12 KiB
Text
284 lines
12 KiB
Text
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2006 AMD
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## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
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##
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## Copyright (C) 2006 MSI
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## Written by bxshi <bingxunshi@gmail.com> for MSI.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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##
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## Compute the location and size of where this firmware image
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## (coreboot plus bootloader) will live in the boot rom chip.
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##
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if USE_FALLBACK_IMAGE
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default ROM_SECTION_SIZE = FALLBACK_SIZE
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default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
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else
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default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
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default ROM_SECTION_OFFSET = 0
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end
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##
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## Compute the start location and size size of
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## The coreboot bootloader.
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##
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default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
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default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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##
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## Compute where this copy of coreboot will start in the boot rom
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##
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default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
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##
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## Compute a range of ROM that can cached to speed up coreboot,
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## execution speed.
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##
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## XIP_ROM_SIZE must be a power of 2.
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## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
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##
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default XIP_ROM_SIZE=65536
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default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
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arch i386 end
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##
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## Build the objects we have code for in this directory.
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##
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driver mainboard.o
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#dir /drivers/si/3114
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#needed by irq_tables and mptable and acpi_tables
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object get_bus_conf.o
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if HAVE_MP_TABLE
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object mptable.o
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end
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if HAVE_PIRQ_TABLE
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object irq_tables.o
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end
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if CONFIG_USE_INIT
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# compile cache_as_ram.c to auto.o
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makerule ./cache_as_ram_auto.o
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depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
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action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
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end
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else
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#compile cache_as_ram.c to auto.inc
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makerule ./cache_as_ram_auto.inc
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depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
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action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
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action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
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action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
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end
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end
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##
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## Build our 16 bit and 32 bit coreboot entry code
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##
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/entry16.inc
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ldscript /cpu/x86/16bit/entry16.lds
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end
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mainboardinit cpu/x86/32bit/entry32.inc
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if CONFIG_USE_INIT
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ldscript /cpu/x86/32bit/entry32.lds
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end
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if CONFIG_USE_INIT
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ldscript /cpu/amd/car/cache_as_ram.lds
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end
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##
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## Build our reset vector (This is where coreboot is entered)
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##
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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##
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## Include an id string (For safe flashing)
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##
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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##
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## Setup Cache-As-Ram
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##
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mainboardinit cpu/amd/car/cache_as_ram.inc
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###
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### This is the early phase of coreboot startup
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### Things are delicate and we test to see if we should
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### failover to another image.
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###
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if USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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end
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###
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### O.k. We aren't just an intermediary anymore!
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###
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##
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## Setup RAM
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##
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if CONFIG_USE_INIT
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initobject cache_as_ram_auto.o
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else
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mainboardinit ./cache_as_ram_auto.inc
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end
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##
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## Include the secondary Configuration files
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##
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config chip.h
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# sample config for amd/serengeti_cheetah
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chip northbridge/amd/amdk8/root_complex
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device apic_cluster 0 on
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chip cpu/amd/socket_F
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device apic 0 on end
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end
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end
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device pci_domain 0 on
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chip northbridge/amd/amdk8
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device pci 18.0 on end
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device pci 18.0 on end
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device pci 18.0 on # northbridge
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# devices on link 0
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chip southbridge/broadcom/bcm5780 # HT2000
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device pci 0.0 on end # PXB 1 0x0130
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device pci 1.0 on # PXB 2 0x0130
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device pci 4.0 on end # GB E 0x1668 vid = 0x14e4
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device pci 4.1 on end # GB E 0x1669 vid = 0x14e4
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end
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device pci 2.0 on end # PCI E 1 #0x0132
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device pci 3.0 on end # PCI E 2
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device pci 4.0 on end # PCI E 3
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device pci 5.0 on end # PCI E 4
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end
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chip southbridge/broadcom/bcm5785 # HT1000
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device pci 0.0 on # HT PXB 0x0036
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device pci d.0 on end # PPBX 0x0104
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device pci e.0 on end # SATA 0x024a
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device pci e.1 on end # SATA 0x024a bx_a001
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device pci e.2 on end # SATA 0x024a bx_a001
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device pci e.3 on end # SATA 0x024a bx_a001
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end
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device pci 1.0 on # Legacy pci main 0x0205
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end
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device pci 1.1 on end # IDE 0x0214
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device pci 1.2 on # LPC 0x0234
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chip superio/nsc/pc87417
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device pnp 2e.0 off # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 off # Parallel Port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 2e.2 off # Com 2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.3 on # Com 1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.4 off end # SWC
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device pnp 2e.5 off end # Mouse
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device pnp 2e.6 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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end
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device pnp 2e.7 off end # GPIO
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device pnp 2e.f off end # XBUS
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device pnp 2e.10 on #RTC
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io 0x60 = 0x70
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io 0x62 = 0x72
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end
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end
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end
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device pci 1.3 on end # WDTimer 0x0238
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device pci 1.4 on end # XIOAPIC0 0x0235
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device pci 1.5 on end # XIOAPIC1
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device pci 1.6 on end # XIOAPIC2
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device pci 2.0 on end # USB 0x0223
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device pci 2.1 on end # USB
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device pci 2.2 on end # USB
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#when HT_CHAIN_END_UNITID_BASE (0,1) < HT_CHAIN_UNITID_BASE (6,,,,),
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chip drivers/pci/onboard
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device pci 3.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address
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# if HT_CHAIN_END_UNITID_BASE=0, it is 4, if HT_CHAIN_END_UNITID_BASE=1, it is 3
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register "rom_address" = "0xfff80000"
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end
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#bx_a013+ start
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#chip drivers/pci/onboard #SATA2
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# device pci 5.0 on end
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# device pci 5.1 on end
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# device pci 5.2 on end
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# device pci 5.3 on end
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#end
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#bx_a013+ end
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end
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#when HT_CHAIN_END_UNITID_BASE > HT_CHAIN_UNITID_BASE (6, ,,,,)
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# chip drivers/pci/onboard
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# device pci 0.0 on end # fake, will be disabled
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# end
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# chip drivers/pci/onboard
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# device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed
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# register "rom_address" = "0xfff80000"
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# end
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end # device pci 18.0
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device pci 18.1 on end
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device pci 18.2 on end
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device pci 18.3 on end
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end # amdk8
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end #pci_domain
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# chip drivers/generic/debug
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# device pnp 0.0 off end # chip name
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# device pnp 0.1 on end # pci_regs_all
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# device pnp 0.2 off end # mem
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# device pnp 0.3 off end # cpuid
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# device pnp 0.4 off end # smbus_regs_all
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# device pnp 0.5 off end # dual core msr
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# device pnp 0.6 off end # cache size
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# device pnp 0.7 off end # tsc
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# end
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end
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