4513020064
The initial timestamps are now pushed on the stack when entering the romstage C code. Tested on Asus P5QC. Change-Id: I88e972caafff5c53d8e68e85415f920c7341b92d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
39 lines
1 KiB
C
39 lines
1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include "i82801jx.h"
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static void enable_spi_prefetch(void)
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{
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u8 reg8;
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pci_devfn_t dev;
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dev = PCI_DEV(0, 0x1f, 0);
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reg8 = pci_read_config8(dev, 0xdc);
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reg8 &= ~(3 << 2);
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reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
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pci_write_config8(dev, 0xdc, reg8);
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}
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static void bootblock_southbridge_init(void)
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{
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enable_spi_prefetch();
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/* Enable RCBA */
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pci_write_config32(PCI_DEV(0, 0x1f, 0), D31F0_RCBA,
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(uintptr_t)DEFAULT_RCBA | 1);
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}
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