74ad66cdc1
Everything else needs to be done by lpc.c Problem was that early settings survived, because the lpc.c is doing ORs only... Hence we decode quite a lot and even strange ranges like IO port 0x4600 etc... Also, if some port which does not fit to predefined set is requested, like 0x290 for Hardware monitor, the wide port is done, but in our case it has range 512 bytes which means we decode in fact 0x290 - 0x490. And if we hit GPU in the 0x3bx range I receive MCE exception if I do isadump -f 0x300 which is bad. Therefore If I detect that the requested range is small (16 bytes) I additionally set the small wide io region so only 16 bytes is decoded. While at it, I fix spelling typos and I init the regs so we don't write random garbage to regs even if we don't enable them later. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6343 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
253 lines
6.7 KiB
C
253 lines
6.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pnp.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <pc80/mc146818rtc.h>
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#include <pc80/isa-dma.h>
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#include <bitops.h>
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#include <arch/io.h>
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#include "sb800.h"
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static void lpc_init(device_t dev)
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{
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u8 byte;
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u32 dword;
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device_t sm_dev;
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/* Enable the LPC Controller */
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sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
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dword = pci_read_config32(sm_dev, 0x64);
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dword |= 1 << 20;
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pci_write_config32(sm_dev, 0x64, dword);
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/* Initialize isa dma */
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isa_dma_init();
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/* Enable DMA transaction on the LPC bus */
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byte = pci_read_config8(dev, 0x40);
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byte |= (1 << 2);
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pci_write_config8(dev, 0x40, byte);
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/* Disable the timeout mechanism on LPC */
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byte = pci_read_config8(dev, 0x48);
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byte &= ~(1 << 7);
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pci_write_config8(dev, 0x48, byte);
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/* Disable LPC MSI Capability */
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byte = pci_read_config8(dev, 0x78);
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byte &= ~(1 << 1);
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byte &= ~(1 << 0); /* Keep the old way. i.e., when bus master/DMA cycle is going
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on on LPC, it holds PCI grant, so no LPC slave cycle can
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interrupt and visit LPC. */
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pci_write_config8(dev, 0x78, byte);
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/* bit0: Enable prefetch a cacheline (64 bytes) when Host reads code from SPI rom */
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/* bit3: Fix SPI_CS# timing issue when running at 66M. TODO:A12. */
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byte = pci_read_config8(dev, 0xBB);
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byte |= 1 << 0 | 1 << 3;
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pci_write_config8(dev, 0xBB, byte);
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}
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static void sb800_lpc_read_resources(device_t dev)
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{
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struct resource *res;
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/* Get the normal pci resources of this device */
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pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */
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pci_get_resource(dev, 0xA0); /* SPI ROM base address */
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/* Add an extra subtractive resource for both memory and I/O. */
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res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
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res->base = 0;
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res->size = 0x1000;
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res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
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IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
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res->base = 0xff800000;
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res->size = 0x00800000; /* 8 MB for flash */
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res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
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IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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//res = new_resource(dev, 3); /* IOAPIC */
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//res->base = 0xfec00000;
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//res->size = 0x00001000;
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//res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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compact_resources(dev);
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}
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static void sb800_lpc_set_resources(struct device *dev)
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{
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struct resource *res;
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pci_dev_set_resources(dev);
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/* Specical case. SPI Base Address. The SpiRomEnable should be set. */
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res = find_resource(dev, 0xA0);
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pci_write_config32(dev, 0xA0, res->base | 1 << 1);
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}
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/**
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* @brief Enable resources for children devices
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*
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* @param dev the device whos children's resources are to be enabled
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*
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*/
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static void sb800_lpc_enable_childrens_resources(device_t dev)
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{
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struct bus *link;
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u32 reg, reg_x;
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int var_num = 0;
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u16 reg_var[3] = {0x0, 0x0, 0x0};
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u8 wiosize = pci_read_config8(dev, 0x74);
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reg = pci_read_config32(dev, 0x44);
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reg_x = pci_read_config32(dev, 0x48);
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for (link = dev->link_list; link; link = link->next) {
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device_t child;
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for (child = link->children; child;
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child = child->sibling) {
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if (child->enabled
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&& (child->path.type == DEVICE_PATH_PNP)) {
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struct resource *res;
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for (res = child->resource_list; res; res = res->next) {
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u32 base, end; /* don't need long long */
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if (!(res->flags & IORESOURCE_IO))
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continue;
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base = res->base;
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end = resource_end(res);
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printk(BIOS_DEBUG, "sb800 lpc decode:%s, base=0x%08x, end=0x%08x\n",
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dev_path(child), base, end);
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switch (base) {
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case 0x60: /* KB */
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case 0x64: /* MS */
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reg |= (1 << 29);
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break;
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case 0x3f8: /* COM1 */
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reg |= (1 << 6);
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break;
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case 0x2f8: /* COM2 */
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reg |= (1 << 7);
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break;
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case 0x378: /* Parallel 1 */
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reg |= (1 << 0);
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reg |= (1 << 1); /* + 0x778 for ECP */
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break;
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case 0x3f0: /* FD0 */
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reg |= (1 << 26);
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break;
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case 0x220: /* Audio 0 */
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reg |= (1 << 8);
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break;
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case 0x300: /* Midi 0 */
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reg |= (1 << 18);
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break;
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case 0x400:
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reg_x |= (1 << 16);
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break;
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case 0x480:
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reg_x |= (1 << 17);
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break;
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case 0x500:
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reg_x |= (1 << 18);
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break;
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case 0x580:
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reg_x |= (1 << 19);
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break;
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case 0x4700:
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reg_x |= (1 << 22);
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break;
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case 0xfd60:
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reg_x |= (1 << 23);
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break;
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default:
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if (var_num >= 3)
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continue; /* only 3 var ; compact them ? */
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switch (var_num) {
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case 0:
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reg_x |= (1 << 2);
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if ((end - base) < 16)
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wiosize |= (1 << 0);
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break;
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case 1:
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reg_x |= (1 << 24);
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if ((end - base) < 16)
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wiosize |= (1 << 2);
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break;
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case 2:
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reg_x |= (1 << 25);
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reg_x |= (1 << 24);
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if ((end - base) < 16)
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wiosize |= (1 << 3);
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break;
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}
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reg_var[var_num++] =
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base & 0xffff;
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}
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}
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}
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}
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}
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pci_write_config32(dev, 0x44, reg);
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pci_write_config32(dev, 0x48, reg_x);
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/* Set WideIO for as many IOs found (fall through is on purpose) */
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switch (var_num) {
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case 2:
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pci_write_config16(dev, 0x90, reg_var[2]);
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case 1:
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pci_write_config16(dev, 0x66, reg_var[1]);
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case 0:
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pci_write_config16(dev, 0x64, reg_var[0]);
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break;
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}
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pci_write_config8(dev, 0x74, wiosize);
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}
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static void sb800_lpc_enable_resources(device_t dev)
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{
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pci_dev_enable_resources(dev);
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sb800_lpc_enable_childrens_resources(dev);
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}
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static struct pci_operations lops_pci = {
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.set_subsystem = pci_dev_set_subsystem,
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};
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static struct device_operations lpc_ops = {
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.read_resources = sb800_lpc_read_resources,
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.set_resources = sb800_lpc_set_resources,
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.enable_resources = sb800_lpc_enable_resources,
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.init = lpc_init,
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.scan_bus = scan_static_bus,
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.ops_pci = &lops_pci,
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};
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static const struct pci_driver lpc_driver __pci_driver = {
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.ops = &lpc_ops,
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.vendor = PCI_VENDOR_ID_ATI,
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.device = PCI_DEVICE_ID_ATI_SB800_LPC,
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};
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