coreboot-kgpe-d16/src
Aaron Durbin 7538937d6e rambi: export SPI write-protect GPIO correctly
Bay Trail has 3 banks of gpios. Therefore, in order to
properly identify a gpio the specific bank number as well
as the GPIO within that bank is needed. The SPI
write-protect GPIO is GPIO 6 within the SUS bank (offset
0x2000).

BUG=chrome-os-partner:24324
BUG=chrome-os-partner:24408
BRANCH=None
TEST=Built and booted. Looked at GPIO sysfs in the
     chromeos_acpi directory.

Change-Id: Ic51b5abe3bacf6cf9b6a90cf666f1a63b098a0e3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179195
Reviewed-on: http://review.coreboot.org/4995
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-05-09 05:41:29 +02:00
..
arch Introduce stage-specific architecture for coreboot 2014-05-06 20:23:31 +02:00
console console: Fix UART selection prompt 2014-04-30 23:47:28 +02:00
cpu Introduce stage-specific architecture for coreboot 2014-05-06 20:23:31 +02:00
device Introduce stage-specific architecture for coreboot 2014-05-06 20:23:31 +02:00
drivers drivers/pc80/Kconfig: Do not init PS/2 keyboard if GRUB 2 is chosen as payload 2014-05-02 15:05:07 +02:00
ec Declare recovery and developer modes outside ChromeOS 2014-05-01 15:38:41 +02:00
include Declare get_write_protect_state() without ChromeOS 2014-05-08 16:25:30 +02:00
lib ChromeOS boards: Always build code for bootmode straps 2014-05-08 16:26:58 +02:00
mainboard rambi: export SPI write-protect GPIO correctly 2014-05-09 05:41:29 +02:00
northbridge northbridge/intel/sandybridge/pei_data.h: Fix typo in hig*h*est in comment 2014-05-06 13:55:39 +02:00
soc baytrail: lpe audio device needs memory for its firmware 2014-05-09 05:41:20 +02:00
southbridge AGESA SPI: Fix Kconfig options 2014-04-29 17:31:40 +02:00
superio superio/fintek/f71869ad: Make hwm devicetree configurable 2014-05-08 12:10:55 +02:00
vendorcode Declare get_write_protect_state() without ChromeOS 2014-05-08 16:25:30 +02:00
Kconfig Introduce stage-specific architecture for coreboot 2014-05-06 20:23:31 +02:00