75985f1d0c
OCP platform Tiogapass is a 2-socket server platform, which is based on a chipset including Intel Skylake-SP processors and a Lewisburg PCH. Skylake-SP is a processor in Intel Xeon Scalable Processor family. Following ACPI tables are added: DSDT/SSDT, MADT, FACP, FACS, HPET, MCFG, SLIT, SRAT, DMAR This patchset is tested on a Tiogapass board. It booted with Linux kernel 4.16.0; lscpu command shows all 72 cpus (2 sockets, 18 cores, 2 thread per core); ssh command shows networking is up from Mellanox ConnectX-4 PCIe NIC card. Towards successful gerrit buildbot build, note that: * microcode is in coreboot intel-microcode submodule repo. * IFD binary is included in this patch. * Dummy ME binary is used, as it may take long time for Intel ME binary to be available in public domain. * Fake FSP binary is used, as at this moment the SKX-SP FSP binary is not going to be available in public domain. Known issues (Not intend to address in this initial support for Xeon-SP processors): * c6 state is not supported. * dsdt table is not fully populated, such as processor/socket devices, some PCIe devices. * SMM handlers are not added. Following are some command execution with CentOS booted from local SATA disk: [root@localhost ~]# lscpu Architecture: x86_64 CPU op-mode(s): 32-bit, 64-bit Byte Order: Little Endian CPU(s): 72 On-line CPU(s) list: 0-71 Thread(s) per core: 2 Core(s) per socket: 18 Socket(s): 2 NUMA node(s): 2 Vendor ID: GenuineIntel CPU family: 6 Model: 85 Model name: Intel(R) Xeon(R) Gold 6139 CPU @ 2.30GHz Stepping: 4 CPU MHz: 140.415 BogoMIPS: 4626.46 Virtualization: VT-x L1d cache: 32K L1i cache: 32K L2 cache: 1024K L3 cache: 25344K NUMA node0 CPU(s): 0-17,36-53 NUMA node1 CPU(s): 18-35,54-71 [root@localhost ~]# ifconfig eth0: flags=4163<UP,BROADCAST,RUNNING,MULTICAST> mtu 1500 inet 172.23.68.190 netmask 255.255.0.0 broadcast 172.23.255.255 inet6 2620:10d:c082:9063:268a:7ff:fe57:5af0 prefixlen 64 //cut inet6 fe80::268a:7ff:fe57:5af0 prefixlen 64 scopeid 0x20<link> inet6 2620:10d:c082:9063::5d2 prefixlen 128 scopeid 0x0<global> ether 24:8a:07:57:5a:f0 txqueuelen 1000 (Ethernet) RX packets 84249 bytes 6371591 (6.0 MiB) RX errors 0 dropped 0 overruns 0 frame 0 TX packets 8418 bytes 748781 (731.2 KiB) TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0 lo: flags=73<UP,LOOPBACK,RUNNING> mtu 65536 inet 127.0.0.1 netmask 255.0.0.0 inet6 ::1 prefixlen 128 scopeid 0x10<host> loop txqueuelen 1000 (Local Loopback) RX packets 613 bytes 63906 (62.4 KiB) RX errors 0 dropped 0 overruns 0 frame 0 TX packets 613 bytes 63906 (62.4 KiB) TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0 [root@localhost ~]# cbmem 36 entries total: // Lines were cut to avoid checkpatch.pl warnings Total Time: 96,243,882,140,175,829 Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Tested-by: johnny_lin@wiwynn.com Change-Id: I29868f03037d1887b90dfb19d15aee83c456edce Reviewed-on: https://review.coreboot.org/c/coreboot/+/38549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> |
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3rdparty | ||
Documentation | ||
LICENSES | ||
configs | ||
payloads | ||
src | ||
util | ||
.checkpatch.conf | ||
.clang-format | ||
.editorconfig | ||
.gitignore | ||
.gitmodules | ||
.gitreview | ||
AUTHORS | ||
COPYING | ||
MAINTAINERS | ||
Makefile | ||
Makefile.inc | ||
README.md | ||
gnat.adc | ||
toolchain.inc |
README.md
coreboot README
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
Payloads
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
Supported Hardware
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
Build Requirements
- make
- gcc / g++
Because Linux distribution compilers tend to use lots of patches. coreboot
does lots of "unusual" things in its build system, some of which break due
to those patches, sometimes by gcc aborting, sometimes - and that's worse -
by generating broken object code.
Two options: use our toolchain (eg. make crosstools-i386) or enable the
ANY_TOOLCHAIN
Kconfig option if you're feeling lucky (no support in this case). - iasl (for targets with ACPI support)
- pkg-config
- libssl-dev (openssl)
Optional:
- doxygen (for generating/viewing documentation)
- gdb (for better debugging facilities on some targets)
- ncurses (for
make menuconfig
andmake nconfig
) - flex and bison (for regenerating parsers)
Building coreboot
Please consult https://www.coreboot.org/Build_HOWTO for details.
Testing coreboot Without Modifying Your Hardware
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Website and Mailing List
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
Copyright and License
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.